Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES
Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outs...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-08-01
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| Series: | Sensors |
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| Online Access: | https://www.mdpi.com/1424-8220/21/16/5655 |
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| author | Ignacio Algredo-Badillo Kelsey A. Ramírez-Gutiérrez Luis Alberto Morales-Rosales Daniel Pacheco Bautista Claudia Feregrino-Uribe |
| author_facet | Ignacio Algredo-Badillo Kelsey A. Ramírez-Gutiérrez Luis Alberto Morales-Rosales Daniel Pacheco Bautista Claudia Feregrino-Uribe |
| author_sort | Ignacio Algredo-Badillo |
| collection | DOAJ |
| description | Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outside the vehicle. The AES algorithm has been widely applied to protect communications in onboard networks and outside the vehicle. Hardware implementations use techniques such as iterative, parallel, unrolled, and pipeline architectures. Nevertheless, the use of AES does not guarantee secure communication, because previous works have proved that implementations of secret key cryptosystems, such as AES, in hardware are sensitive to differential fault analysis. Moreover, it has been demonstrated that even a single fault during encryption or decryption could cause a large number of errors in encrypted or decrypted data. Although techniques such as iterative and parallel architectures have been explored for fault detection to protect AES encryption and decryption, it is necessary to explore other techniques such as pipelining. Furthermore, balancing a high throughput, reducing low power consumption, and using fewer hardware resources in the pipeline design are great challenges, and they are more difficult when considering fault detection and correction. In this research, we propose a novel hybrid pipeline hardware architecture focusing on error and fault detection for the AES cryptographic algorithm. The architecture is hybrid because it combines hardware and time redundancy through a pipeline structure, analyzing and balancing the critical path and distributing the processing elements within each stage. The main contribution is to present a pipeline structure for ciphering five times on the same data blocks, implementing a voting module to verify when an error occurs or when output has correct cipher data, optimizing the process, and using a decision tree to reduce the complexity of all combinations required for evaluating. The architecture is analyzed and implemented on several FPGA technologies, and it reports a throughput of 0.479 Gbps and an efficiency of 0.336 Mbps/LUT when a Virtex-7 is used. |
| first_indexed | 2024-03-10T08:23:30Z |
| format | Article |
| id | doaj.art-7e2adc596308437facadf76bda84a8fd |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-03-10T08:23:30Z |
| publishDate | 2021-08-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-7e2adc596308437facadf76bda84a8fd2023-11-22T09:43:34ZengMDPI AGSensors1424-82202021-08-012116565510.3390/s21165655Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AESIgnacio Algredo-Badillo0Kelsey A. Ramírez-Gutiérrez1Luis Alberto Morales-Rosales2Daniel Pacheco Bautista3Claudia Feregrino-Uribe4CONACYT-Instituto Nacional de Astrofísica, Óptica y Electrónica, Puebla 72840, MexicoCONACYT-Instituto Nacional de Astrofísica, Óptica y Electrónica, Puebla 72840, MexicoFaculty of Civil Engineering, CONACYT-Universidad Michoacana de San Nicolás de Hidalgo, Morelia 58000, MexicoDepartamento de Ingeniería en Computación, Universidad del Istmo, Campus Tehuantepec, Oaxaca 70760, MexicoInstituto Nacional de Astrofísica, Óptica y Electrónica, Puebla 72840, MexicoCurrently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outside the vehicle. The AES algorithm has been widely applied to protect communications in onboard networks and outside the vehicle. Hardware implementations use techniques such as iterative, parallel, unrolled, and pipeline architectures. Nevertheless, the use of AES does not guarantee secure communication, because previous works have proved that implementations of secret key cryptosystems, such as AES, in hardware are sensitive to differential fault analysis. Moreover, it has been demonstrated that even a single fault during encryption or decryption could cause a large number of errors in encrypted or decrypted data. Although techniques such as iterative and parallel architectures have been explored for fault detection to protect AES encryption and decryption, it is necessary to explore other techniques such as pipelining. Furthermore, balancing a high throughput, reducing low power consumption, and using fewer hardware resources in the pipeline design are great challenges, and they are more difficult when considering fault detection and correction. In this research, we propose a novel hybrid pipeline hardware architecture focusing on error and fault detection for the AES cryptographic algorithm. The architecture is hybrid because it combines hardware and time redundancy through a pipeline structure, analyzing and balancing the critical path and distributing the processing elements within each stage. The main contribution is to present a pipeline structure for ciphering five times on the same data blocks, implementing a voting module to verify when an error occurs or when output has correct cipher data, optimizing the process, and using a decision tree to reduce the complexity of all combinations required for evaluating. The architecture is analyzed and implemented on several FPGA technologies, and it reports a throughput of 0.479 Gbps and an efficiency of 0.336 Mbps/LUT when a Virtex-7 is used.https://www.mdpi.com/1424-8220/21/16/5655error detectionerror correctiondecision treepipeline architectureAES security |
| spellingShingle | Ignacio Algredo-Badillo Kelsey A. Ramírez-Gutiérrez Luis Alberto Morales-Rosales Daniel Pacheco Bautista Claudia Feregrino-Uribe Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES Sensors error detection error correction decision tree pipeline architecture AES security |
| title | Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES |
| title_full | Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES |
| title_fullStr | Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES |
| title_full_unstemmed | Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES |
| title_short | Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES |
| title_sort | hybrid pipeline hardware architecture based on error detection and correction for aes |
| topic | error detection error correction decision tree pipeline architecture AES security |
| url | https://www.mdpi.com/1424-8220/21/16/5655 |
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