| Summary: | This paper discusses in detail the effects of Sub-10nm fin-width (Wfin) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the transconductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm Wfin regime, cannot be improved just by Wfin scaling but by optimizing source/drain resistance, gate dielectric thickness together with the Wfin scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.
|
|---|