Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis
This paper discusses in detail the effects of Sub-10nm fin-width (Wfin) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the transconductance degrades and output conductance improves with the reduction in fin-width. Through different analog perf...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2019-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8794627/ |
| _version_ | 1819121015818551296 |
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| author | Mandar S. Bhoir Thomas Chiarella Lars Ake Ragnarsson Jerome Mitard Valentina Terzeiva Naoto Horiguchi Nihar R. Mohapatra |
| author_facet | Mandar S. Bhoir Thomas Chiarella Lars Ake Ragnarsson Jerome Mitard Valentina Terzeiva Naoto Horiguchi Nihar R. Mohapatra |
| author_sort | Mandar S. Bhoir |
| collection | DOAJ |
| description | This paper discusses in detail the effects of Sub-10nm fin-width (Wfin) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the transconductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm Wfin regime, cannot be improved just by Wfin scaling but by optimizing source/drain resistance, gate dielectric thickness together with the Wfin scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability. |
| first_indexed | 2024-12-22T06:29:51Z |
| format | Article |
| id | doaj.art-7ec5231a8fcc4f308d70b5c2a1896db4 |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2024-12-22T06:29:51Z |
| publishDate | 2019-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-7ec5231a8fcc4f308d70b5c2a1896db42022-12-21T18:35:44ZengIEEEIEEE Journal of the Electron Devices Society2168-67342019-01-0171217122410.1109/JEDS.2019.29345758794627Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed AnalysisMandar S. Bhoir0https://orcid.org/0000-0001-7914-8603Thomas Chiarella1Lars Ake Ragnarsson2Jerome Mitard3Valentina Terzeiva4Naoto Horiguchi5Nihar R. Mohapatra6https://orcid.org/0000-0002-8827-5417Department of Electrical Engineering, Indian Institute of Technology Gandhinagar, Gandhinagar, IndiaLogic Technologies, Interuniversity Microelectronics Center, Leuven, BelgiumLogic Technologies, Interuniversity Microelectronics Center, Leuven, BelgiumLogic Technologies, Interuniversity Microelectronics Center, Leuven, BelgiumLogic Technologies, Interuniversity Microelectronics Center, Leuven, BelgiumLogic Technologies, Interuniversity Microelectronics Center, Leuven, BelgiumDepartment of Electrical Engineering, Indian Institute of Technology Gandhinagar, Gandhinagar, IndiaThis paper discusses in detail the effects of Sub-10nm fin-width (Wfin) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the transconductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm Wfin regime, cannot be improved just by Wfin scaling but by optimizing source/drain resistance, gate dielectric thickness together with the Wfin scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.https://ieeexplore.ieee.org/document/8794627/FinFETsub-10nm fin-widthtechnology scalinganalog/RFvariabilitytransconductance |
| spellingShingle | Mandar S. Bhoir Thomas Chiarella Lars Ake Ragnarsson Jerome Mitard Valentina Terzeiva Naoto Horiguchi Nihar R. Mohapatra Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis IEEE Journal of the Electron Devices Society FinFET sub-10nm fin-width technology scaling analog/RF variability transconductance |
| title | Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis |
| title_full | Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis |
| title_fullStr | Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis |
| title_full_unstemmed | Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis |
| title_short | Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis |
| title_sort | analog performance and its variability in sub 10 nm fin width finfets a detailed analysis |
| topic | FinFET sub-10nm fin-width technology scaling analog/RF variability transconductance |
| url | https://ieeexplore.ieee.org/document/8794627/ |
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