SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges
Neuromorphic processors aim to emulate the biological principles of the brain to achieve high efficiency with low power consumption. However, the lack of flexibility in most neuromorphic architecture designs results in significant performance loss and inefficient memory usage when mapping various ne...
| Main Authors: | , , , , , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Frontiers Media S.A.
2023-06-01
|
| Series: | Frontiers in Neuroscience |
| Subjects: | |
| Online Access: | https://www.frontiersin.org/articles/10.3389/fnins.2023.1187252/full |
| _version_ | 1827918141342089216 |
|---|---|
| author | Guangzhi Tang Kanishkan Vadivel Yingfu Xu Refik Bilgic Kevin Shidqi Paul Detterer Stefano Traferro Mario Konijnenburg Manolis Sifalakis Gert-Jan van Schaik Amirreza Yousefzadeh |
| author_facet | Guangzhi Tang Kanishkan Vadivel Yingfu Xu Refik Bilgic Kevin Shidqi Paul Detterer Stefano Traferro Mario Konijnenburg Manolis Sifalakis Gert-Jan van Schaik Amirreza Yousefzadeh |
| author_sort | Guangzhi Tang |
| collection | DOAJ |
| description | Neuromorphic processors aim to emulate the biological principles of the brain to achieve high efficiency with low power consumption. However, the lack of flexibility in most neuromorphic architecture designs results in significant performance loss and inefficient memory usage when mapping various neural network algorithms. This paper proposes SENECA, a digital neuromorphic architecture that balances the trade-offs between flexibility and efficiency using a hierarchical-controlling system. A SENECA core contains two controllers, a flexible controller (RISC-V) and an optimized controller (Loop Buffer). This flexible computational pipeline allows for deploying efficient mapping for various neural networks, on-device learning, and pre-post processing algorithms. The hierarchical-controlling system introduced in SENECA makes it one of the most efficient neuromorphic processors, along with a higher level of programmability. This paper discusses the trade-offs in digital neuromorphic processor design, explains the SENECA architecture, and provides detailed experimental results when deploying various algorithms on the SENECA platform. The experimental results show that the proposed architecture improves energy and area efficiency and illustrates the effect of various trade-offs in algorithm design. A SENECA core consumes 0.47 mm2 when synthesized in the GF-22 nm technology node and consumes around 2.8 pJ per synaptic operation. SENECA architecture scales up by connecting many cores with a network-on-chip. The SENECA platform and the tools used in this project are freely available for academic research upon request. |
| first_indexed | 2024-03-13T03:38:32Z |
| format | Article |
| id | doaj.art-7fa59a1948cb4dc8abe50ed8ab5f00a5 |
| institution | Directory Open Access Journal |
| issn | 1662-453X |
| language | English |
| last_indexed | 2024-03-13T03:38:32Z |
| publishDate | 2023-06-01 |
| publisher | Frontiers Media S.A. |
| record_format | Article |
| series | Frontiers in Neuroscience |
| spelling | doaj.art-7fa59a1948cb4dc8abe50ed8ab5f00a52023-06-23T12:00:32ZengFrontiers Media S.A.Frontiers in Neuroscience1662-453X2023-06-011710.3389/fnins.2023.11872521187252SENECA: building a fully digital neuromorphic processor, design trade-offs and challengesGuangzhi Tang0Kanishkan Vadivel1Yingfu Xu2Refik Bilgic3Kevin Shidqi4Paul Detterer5Stefano Traferro6Mario Konijnenburg7Manolis Sifalakis8Gert-Jan van Schaik9Amirreza Yousefzadeh10Imec, Eindhoven, NetherlandsImec, Eindhoven, NetherlandsImec, Eindhoven, NetherlandsImec, Leuven, BelgiumImec, Eindhoven, NetherlandsImec, Eindhoven, NetherlandsImec, Eindhoven, NetherlandsImec, Eindhoven, NetherlandsImec, Eindhoven, NetherlandsImec, Eindhoven, NetherlandsImec, Eindhoven, NetherlandsNeuromorphic processors aim to emulate the biological principles of the brain to achieve high efficiency with low power consumption. However, the lack of flexibility in most neuromorphic architecture designs results in significant performance loss and inefficient memory usage when mapping various neural network algorithms. This paper proposes SENECA, a digital neuromorphic architecture that balances the trade-offs between flexibility and efficiency using a hierarchical-controlling system. A SENECA core contains two controllers, a flexible controller (RISC-V) and an optimized controller (Loop Buffer). This flexible computational pipeline allows for deploying efficient mapping for various neural networks, on-device learning, and pre-post processing algorithms. The hierarchical-controlling system introduced in SENECA makes it one of the most efficient neuromorphic processors, along with a higher level of programmability. This paper discusses the trade-offs in digital neuromorphic processor design, explains the SENECA architecture, and provides detailed experimental results when deploying various algorithms on the SENECA platform. The experimental results show that the proposed architecture improves energy and area efficiency and illustrates the effect of various trade-offs in algorithm design. A SENECA core consumes 0.47 mm2 when synthesized in the GF-22 nm technology node and consumes around 2.8 pJ per synaptic operation. SENECA architecture scales up by connecting many cores with a network-on-chip. The SENECA platform and the tools used in this project are freely available for academic research upon request.https://www.frontiersin.org/articles/10.3389/fnins.2023.1187252/fullevent-based neuromorphic processorspiking neural networkarchitectural explorationbio-inspired processingSENECAAI accelerator |
| spellingShingle | Guangzhi Tang Kanishkan Vadivel Yingfu Xu Refik Bilgic Kevin Shidqi Paul Detterer Stefano Traferro Mario Konijnenburg Manolis Sifalakis Gert-Jan van Schaik Amirreza Yousefzadeh SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges Frontiers in Neuroscience event-based neuromorphic processor spiking neural network architectural exploration bio-inspired processing SENECA AI accelerator |
| title | SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges |
| title_full | SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges |
| title_fullStr | SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges |
| title_full_unstemmed | SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges |
| title_short | SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges |
| title_sort | seneca building a fully digital neuromorphic processor design trade offs and challenges |
| topic | event-based neuromorphic processor spiking neural network architectural exploration bio-inspired processing SENECA AI accelerator |
| url | https://www.frontiersin.org/articles/10.3389/fnins.2023.1187252/full |
| work_keys_str_mv | AT guangzhitang senecabuildingafullydigitalneuromorphicprocessordesigntradeoffsandchallenges AT kanishkanvadivel senecabuildingafullydigitalneuromorphicprocessordesigntradeoffsandchallenges AT yingfuxu senecabuildingafullydigitalneuromorphicprocessordesigntradeoffsandchallenges AT refikbilgic senecabuildingafullydigitalneuromorphicprocessordesigntradeoffsandchallenges AT kevinshidqi senecabuildingafullydigitalneuromorphicprocessordesigntradeoffsandchallenges AT pauldetterer senecabuildingafullydigitalneuromorphicprocessordesigntradeoffsandchallenges AT stefanotraferro senecabuildingafullydigitalneuromorphicprocessordesigntradeoffsandchallenges AT mariokonijnenburg senecabuildingafullydigitalneuromorphicprocessordesigntradeoffsandchallenges AT manolissifalakis senecabuildingafullydigitalneuromorphicprocessordesigntradeoffsandchallenges AT gertjanvanschaik senecabuildingafullydigitalneuromorphicprocessordesigntradeoffsandchallenges AT amirrezayousefzadeh senecabuildingafullydigitalneuromorphicprocessordesigntradeoffsandchallenges |