Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s
Wireline receivers continue to target higher data rates, posing great challenges at circuit and architecture levels. Governed by tradeoffs among speed, power consumption, and channel loss (CL), receiver designs can benefit from new methods that push the performance envelope. This paper presents a nu...
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10167779/ |
| _version_ | 1797197398970204160 |
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| author | Behzad Razavi |
| author_facet | Behzad Razavi |
| author_sort | Behzad Razavi |
| collection | DOAJ |
| description | Wireline receivers continue to target higher data rates, posing great challenges at circuit and architecture levels. Governed by tradeoffs among speed, power consumption, and channel loss (CL), receiver designs can benefit from new methods that push the performance envelope. This paper presents a number of techniques that allow non-return-to-zero data rates as high as 40 and 56 Gb/s in 45-nm and 28-nm CMOS technologies, respectively. The prototypes operate with a CL of 19-25 dB and a bit error rate of less than 10−12. |
| first_indexed | 2024-04-24T06:43:20Z |
| format | Article |
| id | doaj.art-8155641d99eb414ea5949429e137a4c6 |
| institution | Directory Open Access Journal |
| issn | 2644-1349 |
| language | English |
| last_indexed | 2024-04-24T06:43:20Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj.art-8155641d99eb414ea5949429e137a4c62024-04-22T20:40:04ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492023-01-01311813310.1109/OJSSCS.2023.329055110167779Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/sBehzad Razavi0https://orcid.org/0000-0003-1168-9205Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA, USAWireline receivers continue to target higher data rates, posing great challenges at circuit and architecture levels. Governed by tradeoffs among speed, power consumption, and channel loss (CL), receiver designs can benefit from new methods that push the performance envelope. This paper presents a number of techniques that allow non-return-to-zero data rates as high as 40 and 56 Gb/s in 45-nm and 28-nm CMOS technologies, respectively. The prototypes operate with a CL of 19-25 dB and a bit error rate of less than 10−12.https://ieeexplore.ieee.org/document/10167779/Continuous-time linear equalizer (CTLE)demultiplexers (DMUX)equalizationfeedforwardSERDESserial links |
| spellingShingle | Behzad Razavi Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s IEEE Open Journal of the Solid-State Circuits Society Continuous-time linear equalizer (CTLE) demultiplexers (DMUX) equalization feedforward SERDES serial links |
| title | Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s |
| title_full | Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s |
| title_fullStr | Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s |
| title_full_unstemmed | Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s |
| title_short | Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s |
| title_sort | design techniques for cmos wireline nrz receivers up to 56 gb s |
| topic | Continuous-time linear equalizer (CTLE) demultiplexers (DMUX) equalization feedforward SERDES serial links |
| url | https://ieeexplore.ieee.org/document/10167779/ |
| work_keys_str_mv | AT behzadrazavi designtechniquesforcmoswirelinenrzreceiversupto56gbs |