Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s
Wireline receivers continue to target higher data rates, posing great challenges at circuit and architecture levels. Governed by tradeoffs among speed, power consumption, and channel loss (CL), receiver designs can benefit from new methods that push the performance envelope. This paper presents a nu...
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10167779/ |