Channel geometry-dependent threshold voltage and transconductance degradation in gate-all-around nanosheet junctionless transistors
The gate-all-around (GAA) nanosheet (NS) junctionless transistor (JLT) is an attractive candidate for advanced technology nodes in CMOS scaling. Here, the channel width-dependent transconductance (gm) degradation and threshold voltage (Vth) shift of GAA NS JLTs were investigated via numerical simula...
Main Author: | Dae-Young Jeon |
---|---|
Format: | Article |
Language: | English |
Published: |
AIP Publishing LLC
2021-05-01
|
Series: | AIP Advances |
Online Access: | http://dx.doi.org/10.1063/5.0035460 |
Similar Items
-
Junctionless nanosheet gate‐all‐around transistors fabricated on void embedded silicon on insulator substrate
by: Zhiqiang Mu, et al.
Published: (2023-02-01) -
Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors
by: Meng-Ju Tsai, et al.
Published: (2019-01-01) -
The effect of channel variation for long channel GaAs junctionless gate-all-around transistor
by: Rasol, M. Faidzal, et al.
Published: (2022) -
Tri-gate junctionless transistors with electrostatically highly doped channel
by: Dae-Young Jeon
Published: (2023-11-01) -
Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates
by: Tung-Yu Liu, et al.
Published: (2015-01-01)