Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device
The design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low <inline-formula> <tex-math n...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10332930/ |
| _version_ | 1797338488910118912 |
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| author | Shaoxin Yu Weiheng Shao Rongsheng Chen Rilin Zhang Xiaoqing Liu Yongjun Wu Bin Zhao |
| author_facet | Shaoxin Yu Weiheng Shao Rongsheng Chen Rilin Zhang Xiaoqing Liu Yongjun Wu Bin Zhao |
| author_sort | Shaoxin Yu |
| collection | DOAJ |
| description | The design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low <inline-formula> <tex-math notation="LaTeX">$R_{\mathrm{ on,sp}}$ </tex-math></inline-formula> (Specific on-resistance) LDMOS device is simulated, designed, and fabricated. The effects on FOM (Figures-of-merits) characters from physical dimensions, including field plate length <inline-formula> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula>, field plate thickness <inline-formula> <tex-math notation="LaTeX">${H}$ </tex-math></inline-formula>, and slot contact width <inline-formula> <tex-math notation="LaTeX">${W}$ </tex-math></inline-formula>, have been analyzed and discussed. The best device structure is proposed through simulation, and a related fabrication process is introduced correspondingly. Finally, the electrical measurement results show that <inline-formula> <tex-math notation="LaTeX">$R_{\mathrm{ on,sp}}$ </tex-math></inline-formula> can achieve as low as 6.9m<inline-formula> <tex-math notation="LaTeX">$\Omega \cdot $ </tex-math></inline-formula>mm2 when the source-drain <inline-formula> <tex-math notation="LaTeX">${BV}$ </tex-math></inline-formula>(Breakdown voltage) arrives at 34.1V, which is improved by 47.1% compared with conventional devices. Furthermore, the TLP (Transmission line pulse) test results indicate that the device owns an ideal SOA (Safe operation area) from both typical devices (W <inline-formula> <tex-math notation="LaTeX">$=\,\,10~\mu \text{m}$ </tex-math></inline-formula>) and very large devices (W = 2mm). |
| first_indexed | 2024-03-08T09:31:58Z |
| format | Article |
| id | doaj.art-8290858fdcf6432eb4b67dbde8228d9c |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2024-03-08T09:31:58Z |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-8290858fdcf6432eb4b67dbde8228d9c2024-01-31T00:00:38ZengIEEEIEEE Journal of the Electron Devices Society2168-67342024-01-0112142210.1109/JEDS.2023.333734110332930Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS DeviceShaoxin Yu0https://orcid.org/0009-0005-1274-3789Weiheng Shao1https://orcid.org/0000-0002-7345-3479Rongsheng Chen2https://orcid.org/0000-0002-7247-8420Rilin Zhang3https://orcid.org/0009-0002-6217-9758Xiaoqing Liu4https://orcid.org/0009-0005-5109-6617Yongjun Wu5https://orcid.org/0009-0000-0468-6933Bin Zhao6School of Microelectronics, South China University of Technology, Guangzhou, ChinaSchool of Microelectronics, South China University of Technology, Guangzhou, ChinaSchool of Microelectronics, South China University of Technology, Guangzhou, ChinaCanSemi Technology Inc., Guangzhou, ChinaSchool of Microelectronics, South China University of Technology, Guangzhou, ChinaCanSemi Technology Inc., Guangzhou, ChinaCanSemi Technology Inc., Guangzhou, ChinaThe design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low <inline-formula> <tex-math notation="LaTeX">$R_{\mathrm{ on,sp}}$ </tex-math></inline-formula> (Specific on-resistance) LDMOS device is simulated, designed, and fabricated. The effects on FOM (Figures-of-merits) characters from physical dimensions, including field plate length <inline-formula> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula>, field plate thickness <inline-formula> <tex-math notation="LaTeX">${H}$ </tex-math></inline-formula>, and slot contact width <inline-formula> <tex-math notation="LaTeX">${W}$ </tex-math></inline-formula>, have been analyzed and discussed. The best device structure is proposed through simulation, and a related fabrication process is introduced correspondingly. Finally, the electrical measurement results show that <inline-formula> <tex-math notation="LaTeX">$R_{\mathrm{ on,sp}}$ </tex-math></inline-formula> can achieve as low as 6.9m<inline-formula> <tex-math notation="LaTeX">$\Omega \cdot $ </tex-math></inline-formula>mm2 when the source-drain <inline-formula> <tex-math notation="LaTeX">${BV}$ </tex-math></inline-formula>(Breakdown voltage) arrives at 34.1V, which is improved by 47.1% compared with conventional devices. Furthermore, the TLP (Transmission line pulse) test results indicate that the device owns an ideal SOA (Safe operation area) from both typical devices (W <inline-formula> <tex-math notation="LaTeX">$=\,\,10~\mu \text{m}$ </tex-math></inline-formula>) and very large devices (W = 2mm).https://ieeexplore.ieee.org/document/10332930/Contact field plate (CFP)figures of merits (FOM)lateral double diffusion metal oxide semiconductor (LDMOS)specific on-resistance (Ron,sp) |
| spellingShingle | Shaoxin Yu Weiheng Shao Rongsheng Chen Rilin Zhang Xiaoqing Liu Yongjun Wu Bin Zhao Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device IEEE Journal of the Electron Devices Society Contact field plate (CFP) figures of merits (FOM) lateral double diffusion metal oxide semiconductor (LDMOS) specific on-resistance (Ron,sp) |
| title | Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device |
| title_full | Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device |
| title_fullStr | Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device |
| title_full_unstemmed | Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device |
| title_short | Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device |
| title_sort | design and simulation optimization of an ultra low specific on resistance ldmos device |
| topic | Contact field plate (CFP) figures of merits (FOM) lateral double diffusion metal oxide semiconductor (LDMOS) specific on-resistance (Ron,sp) |
| url | https://ieeexplore.ieee.org/document/10332930/ |
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