A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit
Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle...
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2023-04-01
|
| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/ell2.12793 |
| _version_ | 1827814957484343296 |
|---|---|
| author | Ya Hai Fei Liu Yongshan Wang Jing Kang |
| author_facet | Ya Hai Fei Liu Yongshan Wang Jing Kang |
| author_sort | Ya Hai |
| collection | DOAJ |
| description | Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. |
| first_indexed | 2024-03-11T23:52:14Z |
| format | Article |
| id | doaj.art-84ff5ff2ed6644bf8f0b59c7d2cd1428 |
| institution | Directory Open Access Journal |
| issn | 0013-5194 1350-911X |
| language | English |
| last_indexed | 2024-03-11T23:52:14Z |
| publishDate | 2023-04-01 |
| publisher | Wiley |
| record_format | Article |
| series | Electronics Letters |
| spelling | doaj.art-84ff5ff2ed6644bf8f0b59c7d2cd14282023-09-19T05:15:53ZengWileyElectronics Letters0013-51941350-911X2023-04-01598n/an/a10.1049/ell2.12793A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuitYa Hai0Fei Liu1Yongshan Wang2Jing Kang3Institute of Microelectronics of the Chinese Academy of Sciences Beijing ChinaInstitute of Microelectronics of the Chinese Academy of Sciences Beijing ChinaInstitute of Microelectronics of the Chinese Academy of Sciences Beijing ChinaInstitute of Microelectronics of the Chinese Academy of Sciences Beijing ChinaAbstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz.https://doi.org/10.1049/ell2.12793clock distribution networksCMOS digital integrated circuitsdelay circuitserror correctionhigh‐speed integrated circuitslogic gates |
| spellingShingle | Ya Hai Fei Liu Yongshan Wang Jing Kang A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit Electronics Letters clock distribution networks CMOS digital integrated circuits delay circuits error correction high‐speed integrated circuits logic gates |
| title | A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit |
| title_full | A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit |
| title_fullStr | A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit |
| title_full_unstemmed | A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit |
| title_short | A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit |
| title_sort | small area and low power all digital duty cycle corrector with de skew circuit |
| topic | clock distribution networks CMOS digital integrated circuits delay circuits error correction high‐speed integrated circuits logic gates |
| url | https://doi.org/10.1049/ell2.12793 |
| work_keys_str_mv | AT yahai asmallareaandlowpoweralldigitaldutycyclecorrectorwithdeskewcircuit AT feiliu asmallareaandlowpoweralldigitaldutycyclecorrectorwithdeskewcircuit AT yongshanwang asmallareaandlowpoweralldigitaldutycyclecorrectorwithdeskewcircuit AT jingkang asmallareaandlowpoweralldigitaldutycyclecorrectorwithdeskewcircuit AT yahai smallareaandlowpoweralldigitaldutycyclecorrectorwithdeskewcircuit AT feiliu smallareaandlowpoweralldigitaldutycyclecorrectorwithdeskewcircuit AT yongshanwang smallareaandlowpoweralldigitaldutycyclecorrectorwithdeskewcircuit AT jingkang smallareaandlowpoweralldigitaldutycyclecorrectorwithdeskewcircuit |