A Simple Cache Emulator for Evaluating Cache Behavior for SMP Systems
Every modern CPU uses a complex memory hierarchy, which consists of multiple cache memory levels. It is very difficult to predict the behavior of this hierarchy for a given program (for details see [1, 2]). The situation is even worse for systems with a shared memory. The most important example is t...
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| Format: | Article |
| Language: | English |
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CTU Central Library
2006-01-01
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| Series: | Acta Polytechnica |
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| Online Access: | https://ojs.cvut.cz/ojs/index.php/ap/article/view/822 |