A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture
In this paper, a performance analytical strategy is proposed for Network-on-Chip router with input buffer architecture. First, an analytical model is developed based on semi-Markov process. For the non-work-conserving router with small buffer size, the model can be used to analyze the schedule de...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Stefan cel Mare University of Suceava
2012-11-01
|
| Series: | Advances in Electrical and Computer Engineering |
| Subjects: | |
| Online Access: | http://dx.doi.org/10.4316/AECE.2012.04003 |
| _version_ | 1818142784659390464 |
|---|---|
| author | WANG, J. LI, Y. LI, H. |
| author_facet | WANG, J. LI, Y. LI, H. |
| author_sort | WANG, J. |
| collection | DOAJ |
| description | In this paper, a performance analytical strategy is proposed for Network-on-Chip router with input buffer architecture. First, an analytical model is developed based on semi-Markov process. For the non-work-conserving router with small buffer size, the model can be used to analyze the schedule delay and the average service time for each buffer when given the related parameters. Then, the packet average delay in router is calculated by using the model. Finally, we validate the effectiveness of our strategy by simulation. By comparing our analytical results to simulation results, we show that our strategy successfully captures the Network-on-Chip router performance and it performs better than the state-of-art technology. Therefore, our strategy can be used as an efficiency performance analytical tool for Network-on-Chip design. |
| first_indexed | 2024-12-11T11:21:17Z |
| format | Article |
| id | doaj.art-85606558c5cb4a9e8cab8465c7e64564 |
| institution | Directory Open Access Journal |
| issn | 1582-7445 1844-7600 |
| language | English |
| last_indexed | 2024-12-11T11:21:17Z |
| publishDate | 2012-11-01 |
| publisher | Stefan cel Mare University of Suceava |
| record_format | Article |
| series | Advances in Electrical and Computer Engineering |
| spelling | doaj.art-85606558c5cb4a9e8cab8465c7e645642022-12-22T01:09:09ZengStefan cel Mare University of SuceavaAdvances in Electrical and Computer Engineering1582-74451844-76002012-11-01124192410.4316/AECE.2012.04003A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer ArchitectureWANG, J.LI, Y.LI, H.In this paper, a performance analytical strategy is proposed for Network-on-Chip router with input buffer architecture. First, an analytical model is developed based on semi-Markov process. For the non-work-conserving router with small buffer size, the model can be used to analyze the schedule delay and the average service time for each buffer when given the related parameters. Then, the packet average delay in router is calculated by using the model. Finally, we validate the effectiveness of our strategy by simulation. By comparing our analytical results to simulation results, we show that our strategy successfully captures the Network-on-Chip router performance and it performs better than the state-of-art technology. Therefore, our strategy can be used as an efficiency performance analytical tool for Network-on-Chip design.http://dx.doi.org/10.4316/AECE.2012.04003Network-on-ChipSemi Markov processmodelingqueuing theorysimulation |
| spellingShingle | WANG, J. LI, Y. LI, H. A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture Advances in Electrical and Computer Engineering Network-on-Chip Semi Markov process modeling queuing theory simulation |
| title | A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture |
| title_full | A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture |
| title_fullStr | A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture |
| title_full_unstemmed | A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture |
| title_short | A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture |
| title_sort | performance analytical strategy for network on chip router with input buffer architecture |
| topic | Network-on-Chip Semi Markov process modeling queuing theory simulation |
| url | http://dx.doi.org/10.4316/AECE.2012.04003 |
| work_keys_str_mv | AT wangj aperformanceanalyticalstrategyfornetworkonchiprouterwithinputbufferarchitecture AT liy aperformanceanalyticalstrategyfornetworkonchiprouterwithinputbufferarchitecture AT lih aperformanceanalyticalstrategyfornetworkonchiprouterwithinputbufferarchitecture AT wangj performanceanalyticalstrategyfornetworkonchiprouterwithinputbufferarchitecture AT liy performanceanalyticalstrategyfornetworkonchiprouterwithinputbufferarchitecture AT lih performanceanalyticalstrategyfornetworkonchiprouterwithinputbufferarchitecture |