Impact of on-chip inductance on power supply integrity
Based on product related scenarios, the impact of on-chip inductance on power supply integrity is analyzed. The impact of varying current profiles is shown to be minimal. In a regular power grid with regular bump connections, the impact of on-chip inductance on the cycle average of the supply voltag...
Main Authors: | M. Eireiner, S. Henzler, X. Zhang, J. Berthold, D. Schmitt-Landsiedel |
---|---|
Format: | Article |
Language: | deu |
Published: |
Copernicus Publications
2008-05-01
|
Series: | Advances in Radio Science |
Online Access: | http://www.adv-radio-sci.net/6/227/2008/ars-6-227-2008.pdf |
Similar Items
-
Power supply network design: a case study driven approach
by: M. Eireiner, et al.
Published: (2007-06-01) -
Timing violations due to <i>V<sub>DD</sub>/V<sub>SS</sub></i> bounce
by: M. Eireiner, et al.
Published: (2006-01-01) -
Impact of Level-Converter on Power-Saving Capability of Clustered Voltage Scaling
by: St. Henzler, et al.
Published: (2005-01-01) -
Theory of circuit block switch-off
by: S. Henzler, et al.
Published: (2004-01-01) -
Gate Leakage Reduction by Clocked Power Supply of Adiabatic Logic Circuits
by: Ph. Teichmann, et al.
Published: (2005-01-01)