Enhanced Reliability of a-IGZO TFTs with a Reduced Feature Size and a Clean Etch-Stopper Layer Structure
Abstract The effects of diffuse Cu+ in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on the microstructure and performance during a clean etch stopper (CL-ES) process and a back channel etch (BCE) process are investigated and compared. The CL-ES layer formed with a clean...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
SpringerOpen
2019-05-01
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| Series: | Nanoscale Research Letters |
| Subjects: | |
| Online Access: | http://link.springer.com/article/10.1186/s11671-019-3001-3 |
| Summary: | Abstract The effects of diffuse Cu+ in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on the microstructure and performance during a clean etch stopper (CL-ES) process and a back channel etch (BCE) process are investigated and compared. The CL-ES layer formed with a clean component, as verified by TOF-SIMS, can protect the a-IGZO layer from the S/D etchant and prevent Cu+ diffusion, which helps reduce the number of accepter-like defects and improve the reliability of the TFTs. The fabricated CL-ES-structured TFTs have a superior output stability (final I ds/initial I ds = 82.2 %) compared to that of the BCE-structured TFTs (53.5%) because they have a better initial SS value (0.09 V/dec vs 0.46 V/dec), and a better final SS value (0.16 V/dec vs 0.24 V/dec) after the high current stress (HCS) evaluation. In particular, the variation in the threshold voltages has a large difference (3.5 V for the CL-ES TFTs and 7.2 V for the BCE TFTs), which means that the CL-ES-structured TFTs have a higher reliability than the BCE-structured TFTs. Therefore, the CL-ES process is expected to promote the widespread application of a-IGZO technology in the semiconductor industry. |
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| ISSN: | 1931-7573 1556-276X |