8-bit softcore microprocessor with dual accumulator designed to be used in FPGA
Context: This paper is presents the design and implementation of an 8-bit softcore RISC microprocessor able to be run on space-optimized FPGA, in order to be used for embedded applications. Method: The design of this microprocessor was developed in Verilog hardware description language and can be i...
| Main Authors: | , , |
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| Format: | Article |
| Language: | Spanish |
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Universidad Distrital Francisco Jose de Caldas
2018-04-01
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| Series: | Tecnura |
| Subjects: | |
| Online Access: | http://revistas.udistrital.edu.co/ojs/index.php/Tecnura/article/view/12976 |
| _version_ | 1819020202841473024 |
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| author | Fernando Martinez Santa William Sáenz Rodríguez Fernando Rivera Sánchez |
| author_facet | Fernando Martinez Santa William Sáenz Rodríguez Fernando Rivera Sánchez |
| author_sort | Fernando Martinez Santa |
| collection | DOAJ |
| description | Context: This paper is presents the design and implementation of an 8-bit softcore RISC microprocessor able to be run on space-optimized FPGA, in order to be used for embedded applications.
Method: The design of this microprocessor was developed in Verilog hardware description language and can be implemented in FPGA from different manufacturers; therefore, the user has only to define the input and output ports according to the type of FPGA. This is an accumulator-type processor, but it has two different accumulators that can be used as pointers for indirect addressing. The processor is Harvard with a RAM of 8x256 bits, and a ROM that can be resized from 17x252 bits to 17x8K bits. Additionally, it has one 8-bit input port, one 8-bit output port, and one 8-bit address port, which means that the processor can address more than 256 8-bit output ports/devices. The same applies for input ports.
Results: The developed processor, named “ZA-SUA,” was compared with PICOBLAZE softcore and other three similar processors of free distribution in the Web, and some improvements over those were found. Criteria such as the Flip Flops used, occupied LUTs, Slices in use, and maximum delay of each processor were analyzed, all these results were obtained from the implementation of the processors in the Xilinx FPGAs.
Conclusions: The designed architecture is composed by two accumulators, which can be used either as source or destination for the operation of the ALU. This fact gives some flexibility to the design, doing it better than a single-accumulator processor, and getting it closer to the register-based processors. |
| first_indexed | 2024-12-21T03:47:28Z |
| format | Article |
| id | doaj.art-86703b8e2a714d61984f68eaf0cb0d81 |
| institution | Directory Open Access Journal |
| issn | 0123-921X 2248-7638 |
| language | Spanish |
| last_indexed | 2024-12-21T03:47:28Z |
| publishDate | 2018-04-01 |
| publisher | Universidad Distrital Francisco Jose de Caldas |
| record_format | Article |
| series | Tecnura |
| spelling | doaj.art-86703b8e2a714d61984f68eaf0cb0d812022-12-21T19:17:03ZspaUniversidad Distrital Francisco Jose de CaldasTecnura0123-921X2248-76382018-04-012256405010.14483/22487638.1297696798-bit softcore microprocessor with dual accumulator designed to be used in FPGAFernando Martinez Santa0William Sáenz Rodríguez1Fernando Rivera Sánchez2Universidad Distrital Francisco José de CaldasIngeniería Eléctrica S.A.SAlcaldía de SoachaContext: This paper is presents the design and implementation of an 8-bit softcore RISC microprocessor able to be run on space-optimized FPGA, in order to be used for embedded applications. Method: The design of this microprocessor was developed in Verilog hardware description language and can be implemented in FPGA from different manufacturers; therefore, the user has only to define the input and output ports according to the type of FPGA. This is an accumulator-type processor, but it has two different accumulators that can be used as pointers for indirect addressing. The processor is Harvard with a RAM of 8x256 bits, and a ROM that can be resized from 17x252 bits to 17x8K bits. Additionally, it has one 8-bit input port, one 8-bit output port, and one 8-bit address port, which means that the processor can address more than 256 8-bit output ports/devices. The same applies for input ports. Results: The developed processor, named “ZA-SUA,” was compared with PICOBLAZE softcore and other three similar processors of free distribution in the Web, and some improvements over those were found. Criteria such as the Flip Flops used, occupied LUTs, Slices in use, and maximum delay of each processor were analyzed, all these results were obtained from the implementation of the processors in the Xilinx FPGAs. Conclusions: The designed architecture is composed by two accumulators, which can be used either as source or destination for the operation of the ALU. This fact gives some flexibility to the design, doing it better than a single-accumulator processor, and getting it closer to the register-based processors.http://revistas.udistrital.edu.co/ojs/index.php/Tecnura/article/view/12976embedded microprocessor, harvard architecture, RISC, softcore, FPGA, Verilog, dual accumulator |
| spellingShingle | Fernando Martinez Santa William Sáenz Rodríguez Fernando Rivera Sánchez 8-bit softcore microprocessor with dual accumulator designed to be used in FPGA Tecnura embedded microprocessor, harvard architecture, RISC, softcore, FPGA, Verilog, dual accumulator |
| title | 8-bit softcore microprocessor with dual accumulator designed to be used in FPGA |
| title_full | 8-bit softcore microprocessor with dual accumulator designed to be used in FPGA |
| title_fullStr | 8-bit softcore microprocessor with dual accumulator designed to be used in FPGA |
| title_full_unstemmed | 8-bit softcore microprocessor with dual accumulator designed to be used in FPGA |
| title_short | 8-bit softcore microprocessor with dual accumulator designed to be used in FPGA |
| title_sort | 8 bit softcore microprocessor with dual accumulator designed to be used in fpga |
| topic | embedded microprocessor, harvard architecture, RISC, softcore, FPGA, Verilog, dual accumulator |
| url | http://revistas.udistrital.edu.co/ojs/index.php/Tecnura/article/view/12976 |
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