Low Power Clock Network Design
Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and l...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2011-05-01
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| Series: | Journal of Low Power Electronics and Applications |
| Subjects: | |
| Online Access: | http://www.mdpi.com/2079-9268/1/1/219/ |
| _version_ | 1828273463950835712 |
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| author | Inna Vaisband Eby G. Friedman Ran Ginosar Avinoam Kolodny |
| author_facet | Inna Vaisband Eby G. Friedman Ran Ginosar Avinoam Kolodny |
| author_sort | Inna Vaisband |
| collection | DOAJ |
| description | Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanced low power clock tree using techniques such as buffer and wire sizing. Existing skew mitigation techniques in tree-based clock distribution networks, however, are not efficient in coping with post design variations; whereas the latest non-tree mesh-based solutions reliably handle skew variations, albeit with a significant increase in dissipated power. Alternatively, crosslink-based methods provide low power and variation-efficient skew solutions. Existing crosslink-based methods, however, only address skew at the network topology level and do not target low power consumption. Different methods to manage skew and skew variations within tree and non-tree clock distribution networks are reviewed and compared in this paper. Guidelines for inserting crosslinks within a buffered low power clock tree are provided. Metrics to determine the most power efficient technique for a given circuit are discussed and verified with simulation. |
| first_indexed | 2024-04-13T06:21:53Z |
| format | Article |
| id | doaj.art-868dd6290e454c8c9ca00170af54ca2a |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-13T06:21:53Z |
| publishDate | 2011-05-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-868dd6290e454c8c9ca00170af54ca2a2022-12-22T02:58:37ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682011-05-011121924610.3390/jlpea1010219Low Power Clock Network DesignInna VaisbandEby G. FriedmanRan GinosarAvinoam KolodnyPower is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanced low power clock tree using techniques such as buffer and wire sizing. Existing skew mitigation techniques in tree-based clock distribution networks, however, are not efficient in coping with post design variations; whereas the latest non-tree mesh-based solutions reliably handle skew variations, albeit with a significant increase in dissipated power. Alternatively, crosslink-based methods provide low power and variation-efficient skew solutions. Existing crosslink-based methods, however, only address skew at the network topology level and do not target low power consumption. Different methods to manage skew and skew variations within tree and non-tree clock distribution networks are reviewed and compared in this paper. Guidelines for inserting crosslinks within a buffered low power clock tree are provided. Metrics to determine the most power efficient technique for a given circuit are discussed and verified with simulation.http://www.mdpi.com/2079-9268/1/1/219/low powerskewskew variationcrosslinksmeshtopologies |
| spellingShingle | Inna Vaisband Eby G. Friedman Ran Ginosar Avinoam Kolodny Low Power Clock Network Design Journal of Low Power Electronics and Applications low power skew skew variation crosslinks mesh topologies |
| title | Low Power Clock Network Design |
| title_full | Low Power Clock Network Design |
| title_fullStr | Low Power Clock Network Design |
| title_full_unstemmed | Low Power Clock Network Design |
| title_short | Low Power Clock Network Design |
| title_sort | low power clock network design |
| topic | low power skew skew variation crosslinks mesh topologies |
| url | http://www.mdpi.com/2079-9268/1/1/219/ |
| work_keys_str_mv | AT innavaisband lowpowerclocknetworkdesign AT ebygfriedman lowpowerclocknetworkdesign AT ranginosar lowpowerclocknetworkdesign AT avinoamkolodny lowpowerclocknetworkdesign |