A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator

A chopper-embedded bandgap reference (BGR) scheme is presented using 0.18 μm CMOS technology for low-frequency noise suppression in the clock generator application. As biasing circuitry produces significant flicker noise, along with thermal noise from passive components, the proposed low-noise chopp...

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Main Authors: Neeru Agarwal, Neeraj Agarwal, Chih-Wen Lu, Masahito Oh-e
Format: Article
Language:English
Published: MDPI AG 2021-09-01
Series:Electronics
Subjects:
Online Access:https://www.mdpi.com/2079-9292/10/18/2257
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author Neeru Agarwal
Neeraj Agarwal
Chih-Wen Lu
Masahito Oh-e
author_facet Neeru Agarwal
Neeraj Agarwal
Chih-Wen Lu
Masahito Oh-e
author_sort Neeru Agarwal
collection DOAJ
description A chopper-embedded bandgap reference (BGR) scheme is presented using 0.18 μm CMOS technology for low-frequency noise suppression in the clock generator application. As biasing circuitry produces significant flicker noise, along with thermal noise from passive components, the proposed low-noise chopper-stabilized BGR circuit was designed and implemented for a wide range of temperature from −40 to 125 °C, including a startup and self-biasing circuit to reduce critical low-frequency noise from the bias circuitry and op amp input offset voltage. The BGR circuit generated a reference voltage of 1.25 V for a supply voltage range of 2.5–3.3 V. The gain of the implemented BGR operational transconductance amplifier is 84.1 dB. A non-overlapping clock circuit was implemented to reduce the clock skew effect, which is also one of the noise contributors. The noise analysis of a chopped bandgap voltage reference was evaluated through cadence periodic steady-state (PSS) analysis and periodic noise (PNoise) analysis. The low-frequency flicker noise was reduced from 1.5 to 0.4 μV/sqrt(Hz) at 1 KHz, with the proposed chopping scheme in the bandgap. Comparisons of the noise performance of the chopper-embedded BGR, with and without a low-pass filter, were also performed, and the results show a further reduction in the overall noise. A reduction in the flicker noise, from 181.3 to 10.26 mV/sqrt(Hz) at 100 KHz, was observed with the filter. All circuit blocks of the proposed BGR scheme were designed and simulated using the EDA tool HSPICE, and layout generation was carried out by Laker. The BGR architecture layout dimensions are 285.25 μm × 125.38 μm.
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spelling doaj.art-87e755bb7b4a40f0aa25a4e179c78fec2023-11-22T12:48:16ZengMDPI AGElectronics2079-92922021-09-011018225710.3390/electronics10182257A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock GeneratorNeeru Agarwal0Neeraj Agarwal1Chih-Wen Lu2Masahito Oh-e3Department of Engineering and System Science, National Tsing Hua University, Hsinchu 300044, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu 300044, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu 300044, TaiwanInstitute of Photonics Technologies, Department of Electrical Engineering, National Tsing Hua University, Hsinchu 300044, TaiwanA chopper-embedded bandgap reference (BGR) scheme is presented using 0.18 μm CMOS technology for low-frequency noise suppression in the clock generator application. As biasing circuitry produces significant flicker noise, along with thermal noise from passive components, the proposed low-noise chopper-stabilized BGR circuit was designed and implemented for a wide range of temperature from −40 to 125 °C, including a startup and self-biasing circuit to reduce critical low-frequency noise from the bias circuitry and op amp input offset voltage. The BGR circuit generated a reference voltage of 1.25 V for a supply voltage range of 2.5–3.3 V. The gain of the implemented BGR operational transconductance amplifier is 84.1 dB. A non-overlapping clock circuit was implemented to reduce the clock skew effect, which is also one of the noise contributors. The noise analysis of a chopped bandgap voltage reference was evaluated through cadence periodic steady-state (PSS) analysis and periodic noise (PNoise) analysis. The low-frequency flicker noise was reduced from 1.5 to 0.4 μV/sqrt(Hz) at 1 KHz, with the proposed chopping scheme in the bandgap. Comparisons of the noise performance of the chopper-embedded BGR, with and without a low-pass filter, were also performed, and the results show a further reduction in the overall noise. A reduction in the flicker noise, from 181.3 to 10.26 mV/sqrt(Hz) at 100 KHz, was observed with the filter. All circuit blocks of the proposed BGR scheme were designed and simulated using the EDA tool HSPICE, and layout generation was carried out by Laker. The BGR architecture layout dimensions are 285.25 μm × 125.38 μm.https://www.mdpi.com/2079-9292/10/18/2257bandgap reference (BGR)chopper circuittemp variationflicker noise
spellingShingle Neeru Agarwal
Neeraj Agarwal
Chih-Wen Lu
Masahito Oh-e
A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator
Electronics
bandgap reference (BGR)
chopper circuit
temp variation
flicker noise
title A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator
title_full A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator
title_fullStr A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator
title_full_unstemmed A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator
title_short A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator
title_sort chopper embedded bgr composite noise reduction circuit for clock generator
topic bandgap reference (BGR)
chopper circuit
temp variation
flicker noise
url https://www.mdpi.com/2079-9292/10/18/2257
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