FPGA-Based Processor Acceleration for Image Processing Applications
FPGA-based embedded image processing systems offer considerable computing resources but present programming challenges when compared to software systems. The paper describes an approach based on an FPGA-based soft processor called Image Processing Processor (IPPro) which can operate up to 337 MHz on...
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Format: | Article |
Language: | English |
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MDPI AG
2019-01-01
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Series: | Journal of Imaging |
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Online Access: | http://www.mdpi.com/2313-433X/5/1/16 |
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author | Fahad Siddiqui Sam Amiri Umar Ibrahim Minhas Tiantai Deng Roger Woods Karen Rafferty Daniel Crookes |
author_facet | Fahad Siddiqui Sam Amiri Umar Ibrahim Minhas Tiantai Deng Roger Woods Karen Rafferty Daniel Crookes |
author_sort | Fahad Siddiqui |
collection | DOAJ |
description | FPGA-based embedded image processing systems offer considerable computing resources but present programming challenges when compared to software systems. The paper describes an approach based on an FPGA-based soft processor called Image Processing Processor (IPPro) which can operate up to 337 MHz on a high-end Xilinx FPGA family and gives details of the dataflow-based programming environment. The approach is demonstrated for a k-means clustering operation and a traffic sign recognition application, both of which have been prototyped on an Avnet Zedboard that has Xilinx Zynq-7000 system-on-chip (SoC). A number of parallel dataflow mapping options were explored giving a speed-up of 8 times for the k-means clustering using 16 IPPro cores, and a speed-up of 9.6 times for the morphology filter operation of the traffic sign recognition using 16 IPPro cores compared to their equivalent ARM-based software implementations. We show that for k-means clustering, the 16 IPPro cores implementation is 57, 28 and 1.7 times more power efficient (fps/W) than ARM Cortex-A7 CPU, nVIDIA GeForce GTX980 GPU and ARM Mali-T628 embedded GPU respectively. |
first_indexed | 2024-12-13T19:33:12Z |
format | Article |
id | doaj.art-87f7d1de1b41416f80384e67cc0552d0 |
institution | Directory Open Access Journal |
issn | 2313-433X |
language | English |
last_indexed | 2024-12-13T19:33:12Z |
publishDate | 2019-01-01 |
publisher | MDPI AG |
record_format | Article |
series | Journal of Imaging |
spelling | doaj.art-87f7d1de1b41416f80384e67cc0552d02022-12-21T23:33:52ZengMDPI AGJournal of Imaging2313-433X2019-01-01511610.3390/jimaging5010016jimaging5010016FPGA-Based Processor Acceleration for Image Processing ApplicationsFahad Siddiqui0Sam Amiri1Umar Ibrahim Minhas2Tiantai Deng3Roger Woods4Karen Rafferty5Daniel Crookes6School of Electronics, Electrical Engineering and Computer Science, Queen’s University Belfast, Belfast BT7 1NN, UKSchool of Computing, Electronics and Maths, Coventry University, Coventry CV1 5FB, UKSchool of Electronics, Electrical Engineering and Computer Science, Queen’s University Belfast, Belfast BT7 1NN, UKSchool of Electronics, Electrical Engineering and Computer Science, Queen’s University Belfast, Belfast BT7 1NN, UKSchool of Electronics, Electrical Engineering and Computer Science, Queen’s University Belfast, Belfast BT7 1NN, UKSchool of Electronics, Electrical Engineering and Computer Science, Queen’s University Belfast, Belfast BT7 1NN, UKSchool of Electronics, Electrical Engineering and Computer Science, Queen’s University Belfast, Belfast BT7 1NN, UKFPGA-based embedded image processing systems offer considerable computing resources but present programming challenges when compared to software systems. The paper describes an approach based on an FPGA-based soft processor called Image Processing Processor (IPPro) which can operate up to 337 MHz on a high-end Xilinx FPGA family and gives details of the dataflow-based programming environment. The approach is demonstrated for a k-means clustering operation and a traffic sign recognition application, both of which have been prototyped on an Avnet Zedboard that has Xilinx Zynq-7000 system-on-chip (SoC). A number of parallel dataflow mapping options were explored giving a speed-up of 8 times for the k-means clustering using 16 IPPro cores, and a speed-up of 9.6 times for the morphology filter operation of the traffic sign recognition using 16 IPPro cores compared to their equivalent ARM-based software implementations. We show that for k-means clustering, the 16 IPPro cores implementation is 57, 28 and 1.7 times more power efficient (fps/W) than ARM Cortex-A7 CPU, nVIDIA GeForce GTX980 GPU and ARM Mali-T628 embedded GPU respectively.http://www.mdpi.com/2313-433X/5/1/16FPGAhardware accelerationprocessor architecturesimage processingheterogeneous computing |
spellingShingle | Fahad Siddiqui Sam Amiri Umar Ibrahim Minhas Tiantai Deng Roger Woods Karen Rafferty Daniel Crookes FPGA-Based Processor Acceleration for Image Processing Applications Journal of Imaging FPGA hardware acceleration processor architectures image processing heterogeneous computing |
title | FPGA-Based Processor Acceleration for Image Processing Applications |
title_full | FPGA-Based Processor Acceleration for Image Processing Applications |
title_fullStr | FPGA-Based Processor Acceleration for Image Processing Applications |
title_full_unstemmed | FPGA-Based Processor Acceleration for Image Processing Applications |
title_short | FPGA-Based Processor Acceleration for Image Processing Applications |
title_sort | fpga based processor acceleration for image processing applications |
topic | FPGA hardware acceleration processor architectures image processing heterogeneous computing |
url | http://www.mdpi.com/2313-433X/5/1/16 |
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