Design of SiO2/4H–SiC MOS interfaces by sputter deposition of SiO2 followed by high-temperature CO2-post deposition annealing
Oxidation of silicon carbide (SiC) is known to induce defects at the interface of the SiO2/SiC system. NO-annealing is a standard industrial method of nitridation, but oxidation may progress during NO-nitridation, which may generate interface defects. Here, we propose a new method of fabricating SiO...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
AIP Publishing LLC
2023-11-01
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| Series: | AIP Advances |
| Online Access: | http://dx.doi.org/10.1063/5.0169573 |
| _version_ | 1797404790062317568 |
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| author | Tae-Hyeon Kil Takuma Kobayashi Takayoshi Shimura Heiji Watanabe |
| author_facet | Tae-Hyeon Kil Takuma Kobayashi Takayoshi Shimura Heiji Watanabe |
| author_sort | Tae-Hyeon Kil |
| collection | DOAJ |
| description | Oxidation of silicon carbide (SiC) is known to induce defects at the interface of the SiO2/SiC system. NO-annealing is a standard industrial method of nitridation, but oxidation may progress during NO-nitridation, which may generate interface defects. Here, we propose a new method of fabricating SiO2/SiC metal-oxide-semiconductor (MOS) devices: sputter deposition of SiO2 in an Ar/N2 gas mixture followed by high-temperature CO2-post deposition annealing to form SiO2 and incorporate nitrogen at the interface while suppressing oxidation of the SiC. We obtained the nitrogen depth profile by performing x-ray photoelectron spectroscopy and confirmed that most of the nitrogen atoms exist at the abrupt interface. While maintaining a low interface state density and good insulating property, we demonstrated much improved reliability of MOS devices compared to conventional NO-annealed samples, thanks to the well-designed SiO2/SiC interface by the proposed method. |
| first_indexed | 2024-03-09T03:00:11Z |
| format | Article |
| id | doaj.art-8a3bd10246da4f56b9f2bbfb4aad03c9 |
| institution | Directory Open Access Journal |
| issn | 2158-3226 |
| language | English |
| last_indexed | 2024-03-09T03:00:11Z |
| publishDate | 2023-11-01 |
| publisher | AIP Publishing LLC |
| record_format | Article |
| series | AIP Advances |
| spelling | doaj.art-8a3bd10246da4f56b9f2bbfb4aad03c92023-12-04T17:18:29ZengAIP Publishing LLCAIP Advances2158-32262023-11-011311115304115304-510.1063/5.0169573Design of SiO2/4H–SiC MOS interfaces by sputter deposition of SiO2 followed by high-temperature CO2-post deposition annealingTae-Hyeon Kil0Takuma Kobayashi1Takayoshi Shimura2Heiji Watanabe3Graduate School of Engineering, Osaka University, Suita, Osaka 565-0871, JapanGraduate School of Engineering, Osaka University, Suita, Osaka 565-0871, JapanGraduate School of Engineering, Osaka University, Suita, Osaka 565-0871, JapanGraduate School of Engineering, Osaka University, Suita, Osaka 565-0871, JapanOxidation of silicon carbide (SiC) is known to induce defects at the interface of the SiO2/SiC system. NO-annealing is a standard industrial method of nitridation, but oxidation may progress during NO-nitridation, which may generate interface defects. Here, we propose a new method of fabricating SiO2/SiC metal-oxide-semiconductor (MOS) devices: sputter deposition of SiO2 in an Ar/N2 gas mixture followed by high-temperature CO2-post deposition annealing to form SiO2 and incorporate nitrogen at the interface while suppressing oxidation of the SiC. We obtained the nitrogen depth profile by performing x-ray photoelectron spectroscopy and confirmed that most of the nitrogen atoms exist at the abrupt interface. While maintaining a low interface state density and good insulating property, we demonstrated much improved reliability of MOS devices compared to conventional NO-annealed samples, thanks to the well-designed SiO2/SiC interface by the proposed method.http://dx.doi.org/10.1063/5.0169573 |
| spellingShingle | Tae-Hyeon Kil Takuma Kobayashi Takayoshi Shimura Heiji Watanabe Design of SiO2/4H–SiC MOS interfaces by sputter deposition of SiO2 followed by high-temperature CO2-post deposition annealing AIP Advances |
| title | Design of SiO2/4H–SiC MOS interfaces by sputter deposition of SiO2 followed by high-temperature CO2-post deposition annealing |
| title_full | Design of SiO2/4H–SiC MOS interfaces by sputter deposition of SiO2 followed by high-temperature CO2-post deposition annealing |
| title_fullStr | Design of SiO2/4H–SiC MOS interfaces by sputter deposition of SiO2 followed by high-temperature CO2-post deposition annealing |
| title_full_unstemmed | Design of SiO2/4H–SiC MOS interfaces by sputter deposition of SiO2 followed by high-temperature CO2-post deposition annealing |
| title_short | Design of SiO2/4H–SiC MOS interfaces by sputter deposition of SiO2 followed by high-temperature CO2-post deposition annealing |
| title_sort | design of sio2 4h sic mos interfaces by sputter deposition of sio2 followed by high temperature co2 post deposition annealing |
| url | http://dx.doi.org/10.1063/5.0169573 |
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