Design and verification of AES cryptographic acceleration engine based on RISC-V
With the rapid development of IoT technology and the widespread deployment of IoT devices, the issue of information security has become increasingly prominent. Cryptography is the key core technology to ensure information security, but the traditional cryptographic algorithm adaptation scheme is dif...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | zho |
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National Computer System Engineering Research Institute of China
2023-02-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000159662 |
| _version_ | 1797448197726011392 |
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| author | Zhang Xiaolei Dai Zibin Guo Pengfei Li Yang |
| author_facet | Zhang Xiaolei Dai Zibin Guo Pengfei Li Yang |
| author_sort | Zhang Xiaolei |
| collection | DOAJ |
| description | With the rapid development of IoT technology and the widespread deployment of IoT devices, the issue of information security has become increasingly prominent. Cryptography is the key core technology to ensure information security, but the traditional cryptographic algorithm adaptation scheme is difficult to balance performance and flexibility, this paper proposes a cryptographic instruction extension scheme to achieve a good balance between the two scheme. Firstly, we analyze the computational aspects of the AES algorithm, and propose a cryptographic instruction extension and acceleration engine design scheme by combining the Hummingbird E203 processor architecture; then we complete hardware and software implementation, build an RTL-level simulation environment and an FPGA board-level verification environment; finally, we perform experimental verification and comparative analysis. The experimental results show that the proposed scheme can achieve about 700% acceleration ratio with only nearly 2% increase in hardware resources, which has high energy efficiency and can be applied in resource-constrained situations such as IoT. |
| first_indexed | 2024-03-09T14:06:59Z |
| format | Article |
| id | doaj.art-8ac364def8e64290b501b0695745f05b |
| institution | Directory Open Access Journal |
| issn | 0258-7998 |
| language | zho |
| last_indexed | 2024-03-09T14:06:59Z |
| publishDate | 2023-02-01 |
| publisher | National Computer System Engineering Research Institute of China |
| record_format | Article |
| series | Dianzi Jishu Yingyong |
| spelling | doaj.art-8ac364def8e64290b501b0695745f05b2023-11-30T03:40:55ZzhoNational Computer System Engineering Research Institute of ChinaDianzi Jishu Yingyong0258-79982023-02-01492394410.16157/j.issn.0258-7998.2230463000159662Design and verification of AES cryptographic acceleration engine based on RISC-VZhang Xiaolei0Dai Zibin1Guo Pengfei2Li Yang3Information Engineering University， Zhengzhou 450001， ChinaInformation Engineering University， Zhengzhou 450001， ChinaInformation Engineering University， Zhengzhou 450001， ChinaInformation Engineering University， Zhengzhou 450001， ChinaWith the rapid development of IoT technology and the widespread deployment of IoT devices, the issue of information security has become increasingly prominent. Cryptography is the key core technology to ensure information security, but the traditional cryptographic algorithm adaptation scheme is difficult to balance performance and flexibility, this paper proposes a cryptographic instruction extension scheme to achieve a good balance between the two scheme. Firstly, we analyze the computational aspects of the AES algorithm, and propose a cryptographic instruction extension and acceleration engine design scheme by combining the Hummingbird E203 processor architecture; then we complete hardware and software implementation, build an RTL-level simulation environment and an FPGA board-level verification environment; finally, we perform experimental verification and comparative analysis. The experimental results show that the proposed scheme can achieve about 700% acceleration ratio with only nearly 2% increase in hardware resources, which has high energy efficiency and can be applied in resource-constrained situations such as IoT.http://www.chinaaet.com/article/3000159662risc-vcryptographic instruction extensionacceleration engineinformation security |
| spellingShingle | Zhang Xiaolei Dai Zibin Guo Pengfei Li Yang Design and verification of AES cryptographic acceleration engine based on RISC-V Dianzi Jishu Yingyong risc-v cryptographic instruction extension acceleration engine information security |
| title | Design and verification of AES cryptographic acceleration engine based on RISC-V |
| title_full | Design and verification of AES cryptographic acceleration engine based on RISC-V |
| title_fullStr | Design and verification of AES cryptographic acceleration engine based on RISC-V |
| title_full_unstemmed | Design and verification of AES cryptographic acceleration engine based on RISC-V |
| title_short | Design and verification of AES cryptographic acceleration engine based on RISC-V |
| title_sort | design and verification of aes cryptographic acceleration engine based on risc v |
| topic | risc-v cryptographic instruction extension acceleration engine information security |
| url | http://www.chinaaet.com/article/3000159662 |
| work_keys_str_mv | AT zhangxiaolei designandverificationofaescryptographicaccelerationenginebasedonriscv AT daizibin designandverificationofaescryptographicaccelerationenginebasedonriscv AT guopengfei designandverificationofaescryptographicaccelerationenginebasedonriscv AT liyang designandverificationofaescryptographicaccelerationenginebasedonriscv |