POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS
A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | Russian |
| Published: |
The United Institute of Informatics Problems of the National Academy of Sciences of Belarus
2016-10-01
|
| Series: | Informatika |
| Online Access: | https://inf.grid.by/jour/article/view/112 |
| _version_ | 1797877391034417152 |
|---|---|
| author | D. I. Cheremisinov L. D. Cheremisinova |
| author_facet | D. I. Cheremisinov L. D. Cheremisinova |
| author_sort | D. I. Cheremisinov |
| collection | DOAJ |
| description | A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis. |
| first_indexed | 2024-04-10T02:16:26Z |
| format | Article |
| id | doaj.art-8d1c4d3d64034f4d9fc080e90ea10cf9 |
| institution | Directory Open Access Journal |
| issn | 1816-0301 |
| language | Russian |
| last_indexed | 2024-04-10T02:16:26Z |
| publishDate | 2016-10-01 |
| publisher | The United Institute of Informatics Problems of the National Academy of Sciences of Belarus |
| record_format | Article |
| series | Informatika |
| spelling | doaj.art-8d1c4d3d64034f4d9fc080e90ea10cf92023-03-13T08:32:17ZrusThe United Institute of Informatics Problems of the National Academy of Sciences of BelarusInformatika1816-03012016-10-01048293111POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTSD. I. Cheremisinov0L. D. Cheremisinova1Объединенный институт проблем информатики НАН БеларусиОбъединенный институт проблем информатики НАН БеларусиA problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.https://inf.grid.by/jour/article/view/112 |
| spellingShingle | D. I. Cheremisinov L. D. Cheremisinova POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS Informatika |
| title | POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS |
| title_full | POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS |
| title_fullStr | POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS |
| title_full_unstemmed | POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS |
| title_short | POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS |
| title_sort | power driven synthesis of combinational circuits on the base of cmos vlsi library elements |
| url | https://inf.grid.by/jour/article/view/112 |
| work_keys_str_mv | AT dicheremisinov powerdrivensynthesisofcombinationalcircuitsonthebaseofcmosvlsilibraryelements AT ldcheremisinova powerdrivensynthesisofcombinationalcircuitsonthebaseofcmosvlsilibraryelements |