Double Node Upset Immune RHBD-14T SRAM Cell for Space and Satellite Applications - Pavan Kumar Mukku; Rohit Lorenzo (IEEE Access, 2023)
Deep sub-micron memory devices play a crucial role in space electronic applications due to their susceptibility to single-event upset and double-node upset types of soft errors. When a charged particle from space hit a scaled memory circuit, the critical charge of sensitive storage nodes drops, and a node upset happens across the storage nodes. This paper describes the soft error immune RHBD-14T SRAM cell (SEI-14T) for space and satellite applications. The SEI-14T memory cell consists of two latch circuits coupled in a self-recovering, state-restoring feedback manner. In addition, SEI-14T memory cell mitigate single event upset (SEU) in all sensitive nodes and a portion of double node upset. By considering the sensitive node area separation approach, the remaining upset pairs were recovered. To show the relative performance of the SEI-14T, the state-of-the-art of other radiation-resistant memory cells, such as the Quatro-10T, RHM-12T, RHD-12T, RSP-14T, RHPD-12T, RH-14T, EDP-12T, and QCCS-12T are considered. Compared to all other mentioned memory cells, SEI-14T has superior write stability, and greater read stability than all other memory cells. Furthermore, at 0.8 V supply voltage, SEI-14T minimizes 23%, 12.28% and 20.82% of read access time, write access time and static power consumption respectively compared to existing memory cells. Moreover, the critical charge of SEI-14T was $8.85× / 6.56× / 3.4× / 5.75× / 2.54× / 2.47× / 1.81× / 1.63× / 1.44× $ times larger than 6T-SRAM/ Quatro-10T/ RHM-12T/ RHD-12T/ RSP-14T/ RHPD-12T/ RH-14T/ EDP-12T/ QCCS-12T memory cells.