Self-adapting midware architecture and development for cross-platform PSS

With continuous evolution of semiconductor process technologies and IC (Integrated Chip) scales, more and more complex functions are integrated. Multi-core multi-thread CPU (Central Processing Unit), multi-dimension NoC (Network on Chip), high speed interfaces, kinds of peripherals and so on IP (Int...

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Main Authors: Wang Feng, Wang Lei, Zhang Lirong
Format: Article
Language:zho
Published: National Computer System Engineering Research Institute of China 2023-01-01
Series:Dianzi Jishu Yingyong
Subjects:
Online Access:http://www.chinaaet.com/article/3000157964
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author Wang Feng
Wang Lei
Zhang Lirong
author_facet Wang Feng
Wang Lei
Zhang Lirong
author_sort Wang Feng
collection DOAJ
description With continuous evolution of semiconductor process technologies and IC (Integrated Chip) scales, more and more complex functions are integrated. Multi-core multi-thread CPU (Central Processing Unit), multi-dimension NoC (Network on Chip), high speed interfaces, kinds of peripherals and so on IP (Intellectual Property) are integrated into SoC (System on Chip). As a result, verification scenarios during IC development become extremely complicated, which leads to great challenges to the SoC development and corresponding verification completeness. Currently PSS (Portable Test Stimulus Standard) has been introduced along with the UVM (Universal Verification Methodology) for generating extensive randomized stimulus with more complicated scenarios.
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spelling doaj.art-8e9a565f212e4d209fffaabae8ec3dc62023-11-30T09:14:31ZzhoNational Computer System Engineering Research Institute of ChinaDianzi Jishu Yingyong0258-79982023-01-01491202510.16157/j.issn.0258-7998.2229623000157964Self-adapting midware architecture and development for cross-platform PSSWang Feng0Wang Lei1Zhang Lirong2Xi′an R&D Institute, New H3C Semiconductor, Xi′an 710075, China)Xi′an R&D Institute, New H3C Semiconductor, Xi′an 710075, China)Xi′an R&D Institute, New H3C Semiconductor, Xi′an 710075, China)With continuous evolution of semiconductor process technologies and IC (Integrated Chip) scales, more and more complex functions are integrated. Multi-core multi-thread CPU (Central Processing Unit), multi-dimension NoC (Network on Chip), high speed interfaces, kinds of peripherals and so on IP (Intellectual Property) are integrated into SoC (System on Chip). As a result, verification scenarios during IC development become extremely complicated, which leads to great challenges to the SoC development and corresponding verification completeness. Currently PSS (Portable Test Stimulus Standard) has been introduced along with the UVM (Universal Verification Methodology) for generating extensive randomized stimulus with more complicated scenarios.http://www.chinaaet.com/article/3000157964icpssmidwareverificationvip
spellingShingle Wang Feng
Wang Lei
Zhang Lirong
Self-adapting midware architecture and development for cross-platform PSS
Dianzi Jishu Yingyong
ic
pss
midware
verification
vip
title Self-adapting midware architecture and development for cross-platform PSS
title_full Self-adapting midware architecture and development for cross-platform PSS
title_fullStr Self-adapting midware architecture and development for cross-platform PSS
title_full_unstemmed Self-adapting midware architecture and development for cross-platform PSS
title_short Self-adapting midware architecture and development for cross-platform PSS
title_sort self adapting midware architecture and development for cross platform pss
topic ic
pss
midware
verification
vip
url http://www.chinaaet.com/article/3000157964
work_keys_str_mv AT wangfeng selfadaptingmidwarearchitectureanddevelopmentforcrossplatformpss
AT wanglei selfadaptingmidwarearchitectureanddevelopmentforcrossplatformpss
AT zhanglirong selfadaptingmidwarearchitectureanddevelopmentforcrossplatformpss