Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs
The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiti...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-05-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/10/1156 |
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| author | Lorenzo Benvenuti Alessandro Catania Giuseppe Manfredini Andrea Ria Massimo Piotto Paolo Bruschi |
| author_facet | Lorenzo Benvenuti Alessandro Catania Giuseppe Manfredini Andrea Ria Massimo Piotto Paolo Bruschi |
| author_sort | Lorenzo Benvenuti |
| collection | DOAJ |
| description | The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi mathvariant="sans-serif">Δ</mi><mi mathvariant="sans-serif">Σ</mi></mrow></semantics></math></inline-formula> modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi mathvariant="sans-serif">Δ</mi><mi mathvariant="sans-serif">Σ</mi></mrow></semantics></math></inline-formula> modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence<sup>TM</sup> design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources. |
| first_indexed | 2024-03-10T11:27:53Z |
| format | Article |
| id | doaj.art-8ecbe50179d540cda80a3367f08d883a |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T11:27:53Z |
| publishDate | 2021-05-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-8ecbe50179d540cda80a3367f08d883a2023-11-21T19:28:57ZengMDPI AGElectronics2079-92922021-05-011010115610.3390/electronics10101156Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCsLorenzo Benvenuti0Alessandro Catania1Giuseppe Manfredini2Andrea Ria3Massimo Piotto4Paolo Bruschi5Department of Information Engineering, University of Pisa, 56122 Pisa, ItalyDepartment of Information Engineering, University of Pisa, 56122 Pisa, ItalyDepartment of Information Engineering, University of Pisa, 56122 Pisa, ItalyDepartment of Information Engineering, University of Pisa, 56122 Pisa, ItalyDepartment of Information Engineering, University of Pisa, 56122 Pisa, ItalyDepartment of Information Engineering, University of Pisa, 56122 Pisa, ItalyThe design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi mathvariant="sans-serif">Δ</mi><mi mathvariant="sans-serif">Σ</mi></mrow></semantics></math></inline-formula> modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi mathvariant="sans-serif">Δ</mi><mi mathvariant="sans-serif">Σ</mi></mrow></semantics></math></inline-formula> modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence<sup>TM</sup> design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.https://www.mdpi.com/2079-9292/10/10/1156ADCdelta-sigma modulatorenergy-harvestinginverter-likeultra-low powerultra-low voltage |
| spellingShingle | Lorenzo Benvenuti Alessandro Catania Giuseppe Manfredini Andrea Ria Massimo Piotto Paolo Bruschi Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs Electronics ADC delta-sigma modulator energy-harvesting inverter-like ultra-low power ultra-low voltage |
| title | Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs |
| title_full | Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs |
| title_fullStr | Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs |
| title_full_unstemmed | Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs |
| title_short | Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs |
| title_sort | design strategies and architectures for ultra low voltage delta sigma adcs |
| topic | ADC delta-sigma modulator energy-harvesting inverter-like ultra-low power ultra-low voltage |
| url | https://www.mdpi.com/2079-9292/10/10/1156 |
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