Design and Implementation of Neural Network in FPGA
This paper constructs fully parallel NN hardware architecture, FPGA has been used to reduce neuron hardware by design the activation function inside the neuron without using lookup table as in most researches, to perform an efficient NN. It consist of two main parts; the first part covers network t...
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| Format: | Article |
| Language: | Arabic |
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Mustansiriyah University/College of Engineering
2012-09-01
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| Series: | Journal of Engineering and Sustainable Development |
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| Online Access: | https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1269 |
| Summary: | This paper constructs fully parallel NN hardware architecture, FPGA has been used to reduce neuron hardware by design the activation function inside the neuron without using lookup table as in most researches, to perform an efficient NN. It consist of two main parts; the first part covers network training using MATLAB program, the second part represents the hardware implementation of the trained network through Xilinx high performance Virtex2 FPGA schematic entry design tools.
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| ISSN: | 2520-0917 2520-0925 |