The Design of a Dynamic Configurable Packet Parser Based on FPGA
To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is redu...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-08-01
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| Series: | Micromachines |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2072-666X/14/8/1560 |
| _version_ | 1797583844647370752 |
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| author | Ying Sun Zhichuan Guo |
| author_facet | Ying Sun Zhichuan Guo |
| author_sort | Ying Sun |
| collection | DOAJ |
| description | To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is reduced by optimizing the state machine and parallel extraction matching. At the same time, we introduce the chain mapping idea and container concept to formulate the matching and extraction rules of table entries and enhance the extensibility of the parser. Furthermore, our system supports dynamic configuration through SDN control, allowing flexible adaptation to diverse scenarios. Our design has been verified and simulated with a cocotb-based framework. The resulting architecture is implemented on Xilinx Ultrascale+ FPGAs and supports a throughput of more than 80 Gbps, with a maximum latency of only 36 nanoseconds for L4 protocol parsing. |
| first_indexed | 2024-03-10T23:43:46Z |
| format | Article |
| id | doaj.art-8f428516378147b79c8571ff33f8e6f4 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-10T23:43:46Z |
| publishDate | 2023-08-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-8f428516378147b79c8571ff33f8e6f42023-11-19T02:13:32ZengMDPI AGMicromachines2072-666X2023-08-01148156010.3390/mi14081560The Design of a Dynamic Configurable Packet Parser Based on FPGAYing Sun0Zhichuan Guo1National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, ChinaNational Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, ChinaTo meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is reduced by optimizing the state machine and parallel extraction matching. At the same time, we introduce the chain mapping idea and container concept to formulate the matching and extraction rules of table entries and enhance the extensibility of the parser. Furthermore, our system supports dynamic configuration through SDN control, allowing flexible adaptation to diverse scenarios. Our design has been verified and simulated with a cocotb-based framework. The resulting architecture is implemented on Xilinx Ultrascale+ FPGAs and supports a throughput of more than 80 Gbps, with a maximum latency of only 36 nanoseconds for L4 protocol parsing.https://www.mdpi.com/2072-666X/14/8/1560FPGApacket parserdynamic configurablelow lantency |
| spellingShingle | Ying Sun Zhichuan Guo The Design of a Dynamic Configurable Packet Parser Based on FPGA Micromachines FPGA packet parser dynamic configurable low lantency |
| title | The Design of a Dynamic Configurable Packet Parser Based on FPGA |
| title_full | The Design of a Dynamic Configurable Packet Parser Based on FPGA |
| title_fullStr | The Design of a Dynamic Configurable Packet Parser Based on FPGA |
| title_full_unstemmed | The Design of a Dynamic Configurable Packet Parser Based on FPGA |
| title_short | The Design of a Dynamic Configurable Packet Parser Based on FPGA |
| title_sort | design of a dynamic configurable packet parser based on fpga |
| topic | FPGA packet parser dynamic configurable low lantency |
| url | https://www.mdpi.com/2072-666X/14/8/1560 |
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