Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation
A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task’s memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory)...
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| Format: | Article |
| Language: | English |
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MDPI AG
2019-06-01
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| Series: | Micromachines |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2072-666X/10/6/371 |
| _version_ | 1818323961601064960 |
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| author | Sunhwa A. Nam Kyungwoon Cho Hyokyung Bahn |
| author_facet | Sunhwa A. Nam Kyungwoon Cho Hyokyung Bahn |
| author_sort | Sunhwa A. Nam |
| collection | DOAJ |
| description | A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task’s memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory) into the task model of the processor’s voltage scaling and adopts power-saving techniques for processor and memory selectively without violating the deadline constraints. Unlike previous work, our model tightly evaluates the worst-case execution time of a task, considering the time delay that may overlap between the processor and memory, thereby reducing the power consumption of real-time systems by 18–88%. |
| first_indexed | 2024-12-13T11:21:01Z |
| format | Article |
| id | doaj.art-8f557ae7a5ea4471a365cee1585c6429 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-12-13T11:21:01Z |
| publishDate | 2019-06-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-8f557ae7a5ea4471a365cee1585c64292022-12-21T23:48:28ZengMDPI AGMicromachines2072-666X2019-06-0110637110.3390/mi10060371mi10060371Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory AllocationSunhwa A. Nam0Kyungwoon Cho1Hyokyung Bahn2Department of Computer Engineering, Ewha University, Seoul 03760, KoreaEmbedded Software Research Center, Ewha University, Seoul 03760, KoreaDepartment of Computer Engineering, Ewha University, Seoul 03760, KoreaA power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task’s memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory) into the task model of the processor’s voltage scaling and adopts power-saving techniques for processor and memory selectively without violating the deadline constraints. Unlike previous work, our model tightly evaluates the worst-case execution time of a task, considering the time delay that may overlap between the processor and memory, thereby reducing the power consumption of real-time systems by 18–88%.https://www.mdpi.com/2072-666X/10/6/371real-time systemdynamic voltage scalingtask placementlow-power techniquenonvolatile memory |
| spellingShingle | Sunhwa A. Nam Kyungwoon Cho Hyokyung Bahn Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation Micromachines real-time system dynamic voltage scaling task placement low-power technique nonvolatile memory |
| title | Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation |
| title_full | Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation |
| title_fullStr | Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation |
| title_full_unstemmed | Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation |
| title_short | Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation |
| title_sort | tight evaluation of real time task schedulability for processor s dvs and nonvolatile memory allocation |
| topic | real-time system dynamic voltage scaling task placement low-power technique nonvolatile memory |
| url | https://www.mdpi.com/2072-666X/10/6/371 |
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