| Summary: | In the VLSI industry, the ability to anticipate variability tolerance is essential to understanding the circuits’ potential future performance. The cadence virtuoso tool is used in this study to assess how PVT fluctuations affect various fin-shaped field effect transistor (FinFET) circuits. In this research, high-performance FinFET-based circuits at 7 nm are discussed with a variation in temperature and voltage. The idea behind the technology is the improvement of power dissipation and delay reduction at the rise of temperature and reduced supply voltage. With the use of a multi-gate predictive model, simulation is carried out employing diverse domino logic at the 7 nm technology node of FinFET files. The proposed set-reset logic circuit and high-speed cascade circuit method shows less power dissipation and delay compared to the existing current mirror footed domino, high-speed clocked delay, and modified high-speed clocked delay with a variation of temperature and supply voltage. For the proposed set-reset logic circuit and high speed cascade circuit, a Monte Carlo simulation is done to find the mean and standard deviation. FinFET simulations are run on the suggested circuit for the reduction of delay for the rise of temperature and reduction of supply voltage from 0.7 V to 0.3 V. In comparison, the proposed method results in a maximum power decrease compared to existing ones. Compared to the existing one, proposed techniques achieve a maximum delay and area reduction.
|
|---|