Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals
This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) <inline-formula> <tex-m...
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9465156/ |
| _version_ | 1818652724574552064 |
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| author | Roman Sotner Ladislav Polak Jan Jerabek Jiri Petrzela Vilem Kledrowetz |
| author_facet | Roman Sotner Ladislav Polak Jan Jerabek Jiri Petrzela Vilem Kledrowetz |
| author_sort | Roman Sotner |
| collection | DOAJ |
| description | This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) <inline-formula> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain. |
| first_indexed | 2024-12-17T02:26:33Z |
| format | Article |
| id | doaj.art-908fc8a4415d4662b002fd4e6b1f0c68 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-17T02:26:33Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-908fc8a4415d4662b002fd4e6b1f0c682022-12-21T22:07:05ZengIEEEIEEE Access2169-35362021-01-019930629307810.1109/ACCESS.2021.30925259465156Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated SignalsRoman Sotner0https://orcid.org/0000-0002-2430-1815Ladislav Polak1https://orcid.org/0000-0001-7084-6210Jan Jerabek2https://orcid.org/0000-0001-9487-5024Jiri Petrzela3https://orcid.org/0000-0001-5286-9574Vilem Kledrowetz4Department of Radio Electronics, FEEC, Brno University of Technology, Brno, Czech RepublicDepartment of Radio Electronics, FEEC, Brno University of Technology, Brno, Czech RepublicDepartment of Telecommunications, FEEC, Brno University of Technology, Brno, Czech RepublicDepartment of Radio Electronics, FEEC, Brno University of Technology, Brno, Czech RepublicDepartment of Microelectronics, FEEC, Brno University of Technology, Brno, Czech RepublicThis work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) <inline-formula> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.https://ieeexplore.ieee.org/document/9465156/All-pass filterCMOS multiplierelectronic adjustmentfrequency demodulationphase detectorphase shifter |
| spellingShingle | Roman Sotner Ladislav Polak Jan Jerabek Jiri Petrzela Vilem Kledrowetz Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals IEEE Access All-pass filter CMOS multiplier electronic adjustment frequency demodulation phase detector phase shifter |
| title | Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals |
| title_full | Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals |
| title_fullStr | Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals |
| title_full_unstemmed | Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals |
| title_short | Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals |
| title_sort | analog multipliers based double output voltage phase detector for low frequency demodulation of frequency modulated signals |
| topic | All-pass filter CMOS multiplier electronic adjustment frequency demodulation phase detector phase shifter |
| url | https://ieeexplore.ieee.org/document/9465156/ |
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