An Event-Driven Self-Clocked Digital Low-Dropout Regulator with Adaptive Frequency Control
Digital low-dropout (DLDO) is widely used for power management in the system-on-chip (SoC) because of its low-voltage operation and process scalability. However, conventional DLDOs suffer from the trade-off between transient response and power consumption of the DLDO and the clock generator. This pa...
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-06-01
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| Series: | Energies |
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| Online Access: | https://www.mdpi.com/1996-1073/16/12/4749 |
| _version_ | 1797595050721411072 |
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| author | Yen-Ming Chen Ching-Jan Chen |
| author_facet | Yen-Ming Chen Ching-Jan Chen |
| author_sort | Yen-Ming Chen |
| collection | DOAJ |
| description | Digital low-dropout (DLDO) is widely used for power management in the system-on-chip (SoC) because of its low-voltage operation and process scalability. However, conventional DLDOs suffer from the trade-off between transient response and power consumption of the DLDO and the clock generator. This paper proposes an event-driven self-clocked DLDO regulator. The proposed low quiescent current (I<sub>Q</sub>) event-driven adaptive frequency clock generator (EACG) adapts its frequency in different load conditions without a current sensor or complex compensation circuit for stable operation in the entire load range. The proposed DLDO does not need any external clocking signal and can maintain low output ripple and low power consumption in the steady-state. The clock-less transient detector (CLTD), consisting of two clock-independent transient detection paths, uses power more efficiently and improves the transient response significantly without sacrificing the power consumption. This work was fabricated in a 40 nm CMOS process with an 0.3 nF on-chip capacitor. The measurement results show that with the step load current between 1 mA and 60 mA, the proposed DLDO achieves a transient recovery time of 220 ns. The total I<sub>Q</sub> of the proposed DLDO is only 26 μA in steady-state, and it achieves stable operation in the entire load range. |
| first_indexed | 2024-03-11T02:30:56Z |
| format | Article |
| id | doaj.art-921340a55c4b48e78fcd94a86532dda1 |
| institution | Directory Open Access Journal |
| issn | 1996-1073 |
| language | English |
| last_indexed | 2024-03-11T02:30:56Z |
| publishDate | 2023-06-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Energies |
| spelling | doaj.art-921340a55c4b48e78fcd94a86532dda12023-11-18T10:13:36ZengMDPI AGEnergies1996-10732023-06-011612474910.3390/en16124749An Event-Driven Self-Clocked Digital Low-Dropout Regulator with Adaptive Frequency ControlYen-Ming Chen0Ching-Jan Chen1Department of Electrical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Rd., Taipei 10617, TaiwanDepartment of Electrical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Rd., Taipei 10617, TaiwanDigital low-dropout (DLDO) is widely used for power management in the system-on-chip (SoC) because of its low-voltage operation and process scalability. However, conventional DLDOs suffer from the trade-off between transient response and power consumption of the DLDO and the clock generator. This paper proposes an event-driven self-clocked DLDO regulator. The proposed low quiescent current (I<sub>Q</sub>) event-driven adaptive frequency clock generator (EACG) adapts its frequency in different load conditions without a current sensor or complex compensation circuit for stable operation in the entire load range. The proposed DLDO does not need any external clocking signal and can maintain low output ripple and low power consumption in the steady-state. The clock-less transient detector (CLTD), consisting of two clock-independent transient detection paths, uses power more efficiently and improves the transient response significantly without sacrificing the power consumption. This work was fabricated in a 40 nm CMOS process with an 0.3 nF on-chip capacitor. The measurement results show that with the step load current between 1 mA and 60 mA, the proposed DLDO achieves a transient recovery time of 220 ns. The total I<sub>Q</sub> of the proposed DLDO is only 26 μA in steady-state, and it achieves stable operation in the entire load range.https://www.mdpi.com/1996-1073/16/12/4749digital low-dropout (DLDO) regulatorevent-drivenlow power consumptionadaptive frequencysystem-on-chip (SoC) |
| spellingShingle | Yen-Ming Chen Ching-Jan Chen An Event-Driven Self-Clocked Digital Low-Dropout Regulator with Adaptive Frequency Control Energies digital low-dropout (DLDO) regulator event-driven low power consumption adaptive frequency system-on-chip (SoC) |
| title | An Event-Driven Self-Clocked Digital Low-Dropout Regulator with Adaptive Frequency Control |
| title_full | An Event-Driven Self-Clocked Digital Low-Dropout Regulator with Adaptive Frequency Control |
| title_fullStr | An Event-Driven Self-Clocked Digital Low-Dropout Regulator with Adaptive Frequency Control |
| title_full_unstemmed | An Event-Driven Self-Clocked Digital Low-Dropout Regulator with Adaptive Frequency Control |
| title_short | An Event-Driven Self-Clocked Digital Low-Dropout Regulator with Adaptive Frequency Control |
| title_sort | event driven self clocked digital low dropout regulator with adaptive frequency control |
| topic | digital low-dropout (DLDO) regulator event-driven low power consumption adaptive frequency system-on-chip (SoC) |
| url | https://www.mdpi.com/1996-1073/16/12/4749 |
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