Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors

The gate resistance is a parasitic element in transistors for RF and millimeter-wave circuits that can negatively impact power gain and noise figure. To develop accurate device models, a reliable measurement methodology is crucial. This article reviews the standard measurement methodology used in th...

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Main Authors: Mario Lauritano, Peter Baumgartner, Ahmet Çağri Ulusoy
Format: Article
Language:English
Published: MDPI AG 2023-07-01
Series:Electronics
Subjects:
Online Access:https://www.mdpi.com/2079-9292/12/14/3011
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author Mario Lauritano
Peter Baumgartner
Ahmet Çağri Ulusoy
author_facet Mario Lauritano
Peter Baumgartner
Ahmet Çağri Ulusoy
author_sort Mario Lauritano
collection DOAJ
description The gate resistance is a parasitic element in transistors for RF and millimeter-wave circuits that can negatively impact power gain and noise figure. To develop accurate device models, a reliable measurement methodology is crucial. This article reviews the standard measurement methodology used in the literature and proposes also an additional method, which is evaluated using suitable test structures in a 16 nm FinFET process. The advantages and disadvantages of the two approaches are discussed along with their respective application scenarios.
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spelling doaj.art-927149f9cca042ba845d856646c15cf82023-11-18T19:04:33ZengMDPI AGElectronics2079-92922023-07-011214301110.3390/electronics12143011Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF TransistorsMario Lauritano0Peter Baumgartner1Ahmet Çağri Ulusoy2Intel Germany, 85579 Neubiberg, GermanyIntel Germany, 85579 Neubiberg, GermanyInstitute of Radio Frequency Engineering and Electronics (IHE), Karlsruhe Institute of Technology (KIT), 76131 Karlsruhe, GermanyThe gate resistance is a parasitic element in transistors for RF and millimeter-wave circuits that can negatively impact power gain and noise figure. To develop accurate device models, a reliable measurement methodology is crucial. This article reviews the standard measurement methodology used in the literature and proposes also an additional method, which is evaluated using suitable test structures in a 16 nm FinFET process. The advantages and disadvantages of the two approaches are discussed along with their respective application scenarios.https://www.mdpi.com/2079-9292/12/14/3011gate resistancecharacterizationde-embeddingradio-frequency MOSFETs (RF MOSFETs)FinFET
spellingShingle Mario Lauritano
Peter Baumgartner
Ahmet Çağri Ulusoy
Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors
Electronics
gate resistance
characterization
de-embedding
radio-frequency MOSFETs (RF MOSFETs)
FinFET
title Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors
title_full Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors
title_fullStr Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors
title_full_unstemmed Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors
title_short Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors
title_sort test structures for the characterization of the gate resistance in 16 nm finfet rf transistors
topic gate resistance
characterization
de-embedding
radio-frequency MOSFETs (RF MOSFETs)
FinFET
url https://www.mdpi.com/2079-9292/12/14/3011
work_keys_str_mv AT mariolauritano teststructuresforthecharacterizationofthegateresistancein16nmfinfetrftransistors
AT peterbaumgartner teststructuresforthecharacterizationofthegateresistancein16nmfinfetrftransistors
AT ahmetcagriulusoy teststructuresforthecharacterizationofthegateresistancein16nmfinfetrftransistors