Comparison of power consumption in pipelined implementations of the BLAKE3 cipher in FPGA devices
This article analyzes the dynamic power losses generated by various hardware implementations of the BLAKE3 hash function. Estimations of the parameters were based on the results of post-route simulations of designs implemented in Xilinx Spartan-7 FPGAs. The algorithm was tested in various hardware o...
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| Format: | Article |
| Language: | English |
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Polish Academy of Sciences
2024-03-01
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| Series: | International Journal of Electronics and Telecommunications |
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| Online Access: | https://journals.pan.pl/Content/130639/PDF/3-4440-Sugier-sk.pdf |