1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs
We present a three-dimensional (3D) DRAM prototype, which is formed using oxide semiconductor FETs (OSFETs) monolithically stacked on a Si CMOS. The OSFETs are composed of a one-layer planar FET and two-layer vertical FETs (VFETs). The 1T1C memory cells in the VFET layers and a primary sense amplifi...
Main Authors: | Takeya Hirose, Yuki Okamoto, Yusuke Komura, Toshiki Mizuguchi, Toshihiko Saito, Minato Ito, Kiyotaka Kimura, Hiroki Inoue, Tatsuya Onuki, Yoshinori Ando, Hiromi Sawai, Tsutomu Murakawa, Hitoshi Kunitake, Hajime Kimura, Takanori Matsuzaki, Makoto Ikeda, Shunpei Yamazaki |
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Format: | Article |
Language: | English |
Published: |
IEEE
2024-01-01
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Series: | IEEE Journal of the Electron Devices Society |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/10457845/ |
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