Generation of address sequences with a given switching activity
The relevance of testing modern computing systems and, first of all, their storage devices is shown. The studies are based on the use of a universal method for generating the address sequences with desired properties for multiple March tests of random access memory devices. The modification of...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | Russian |
| Published: |
The United Institute of Informatics Problems of the National Academy of Sciences of Belarus
2020-03-01
|
| Series: | Informatika |
| Subjects: | |
| Online Access: | https://inf.grid.by/jour/article/view/889 |
| _version_ | 1797877256353218560 |
|---|---|
| author | V. N. Yarmolik N. A. Shevchenko |
| author_facet | V. N. Yarmolik N. A. Shevchenko |
| author_sort | V. N. Yarmolik |
| collection | DOAJ |
| description | The relevance of testing modern computing systems and, first of all, their storage devices is shown. The studies are based on the use of a universal method for generating the address sequences with desired properties for multiple March tests of random access memory devices. The modification of economical method of Antonov and Saleev is used as mathematical model to form Sobol sequences. For this model a structural diagram of its hardware implementation is presented, where the storage device for storing direction numbers is used as the basis. The set of multitudes makes up the generating matrix. It is noted that the form of the generating matrix determines the basic properties of the generated sequences. Mathematical expressions are obtained that make it possible to estimate the limiting values of switching activity, both of the sequence itself and of its individual bits. A technique is proposed for the synthesis of generators of address sequences with a given switching activity both of its individual bits and of the sequence as a whole. Examples of the application of the proposed methods are considered. The applicability of the presented results to the synthesis of test sequence generators with a given switching activity for the purpose of testing storage devices and the formation of controlled random test sequences is substantiated. The results of the practical implementation of address sequence generators are presented and their main characteristics are evaluated. |
| first_indexed | 2024-04-10T02:14:07Z |
| format | Article |
| id | doaj.art-93ca8647e958467cb21f710f8ed94cbb |
| institution | Directory Open Access Journal |
| issn | 1816-0301 |
| language | Russian |
| last_indexed | 2024-04-10T02:14:07Z |
| publishDate | 2020-03-01 |
| publisher | The United Institute of Informatics Problems of the National Academy of Sciences of Belarus |
| record_format | Article |
| series | Informatika |
| spelling | doaj.art-93ca8647e958467cb21f710f8ed94cbb2023-03-13T08:32:24ZrusThe United Institute of Informatics Problems of the National Academy of Sciences of BelarusInformatika1816-03012020-03-01171476210.37661/1816-0301-2020-17-1-47-62878Generation of address sequences with a given switching activityV. N. Yarmolik0N. A. Shevchenko1Belarusian State University of Informatics and RadioelectronicsLichtenberg GymnasiumThe relevance of testing modern computing systems and, first of all, their storage devices is shown. The studies are based on the use of a universal method for generating the address sequences with desired properties for multiple March tests of random access memory devices. The modification of economical method of Antonov and Saleev is used as mathematical model to form Sobol sequences. For this model a structural diagram of its hardware implementation is presented, where the storage device for storing direction numbers is used as the basis. The set of multitudes makes up the generating matrix. It is noted that the form of the generating matrix determines the basic properties of the generated sequences. Mathematical expressions are obtained that make it possible to estimate the limiting values of switching activity, both of the sequence itself and of its individual bits. A technique is proposed for the synthesis of generators of address sequences with a given switching activity both of its individual bits and of the sequence as a whole. Examples of the application of the proposed methods are considered. The applicability of the presented results to the synthesis of test sequence generators with a given switching activity for the purpose of testing storage devices and the formation of controlled random test sequences is substantiated. The results of the practical implementation of address sequence generators are presented and their main characteristics are evaluated.https://inf.grid.by/jour/article/view/889testing of computing systemsmultiple testingaddress sequencesmodified sobol sequencesswitching activity |
| spellingShingle | V. N. Yarmolik N. A. Shevchenko Generation of address sequences with a given switching activity Informatika testing of computing systems multiple testing address sequences modified sobol sequences switching activity |
| title | Generation of address sequences with a given switching activity |
| title_full | Generation of address sequences with a given switching activity |
| title_fullStr | Generation of address sequences with a given switching activity |
| title_full_unstemmed | Generation of address sequences with a given switching activity |
| title_short | Generation of address sequences with a given switching activity |
| title_sort | generation of address sequences with a given switching activity |
| topic | testing of computing systems multiple testing address sequences modified sobol sequences switching activity |
| url | https://inf.grid.by/jour/article/view/889 |
| work_keys_str_mv | AT vnyarmolik generationofaddresssequenceswithagivenswitchingactivity AT nashevchenko generationofaddresssequenceswithagivenswitchingactivity |