DESIGN AND IMPLEMENTATION OF A DIGITAL PHASE LOCKED LOOP FREQUENCY SYNTHESIZER IN THE L BAND
This paper proposes a design and implementation method of DPLL frequency synthesizer system. Such a system offers many advantages such as minimum complex architecture, low power consumption, and a maximum use of large scale integration technology. It can be used in many applications as cordless te...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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University of Baghdad
2024-03-01
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| Series: | Journal of Engineering |
| Online Access: | https://www.joe.uobaghdad.edu.iq/index.php/main/article/view/3401 |
| _version_ | 1797225359189475328 |
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| author | Nasser N. Khamiss AI- Ani Walid A. Mahmoud Riadh A. Mahdy |
| author_facet | Nasser N. Khamiss AI- Ani Walid A. Mahmoud Riadh A. Mahdy |
| author_sort | Nasser N. Khamiss AI- Ani |
| collection | DOAJ |
| description |
This paper proposes a design and implementation method of DPLL frequency synthesizer system. Such a system offers many advantages such as minimum complex architecture, low power consumption, and a maximum use of large scale integration technology. It can be used in many applications as cordless telephones, rnobile radios and other wireless products. A (2.4 - 3.6) GHz frequency range is designed and implemented with a 100KHz frequency step size. A spurious output levels of -70 dBc, an output power should be greater than 10 dBm, and a phase noise less then (-100) dBc/Hz at 100 kHz ofl'set from the carier are considered in our design. The channel
selection is guided by digital gating circuits with thumbwheel switches. An option of PI\4 modulation of 5 MHz FM bandwidth is also included.
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| first_indexed | 2024-04-24T14:07:45Z |
| format | Article |
| id | doaj.art-94db4fa0cf0740cd9e048040dc1976f9 |
| institution | Directory Open Access Journal |
| issn | 1726-4073 2520-3339 |
| language | English |
| last_indexed | 2024-04-24T14:07:45Z |
| publishDate | 2024-03-01 |
| publisher | University of Baghdad |
| record_format | Article |
| series | Journal of Engineering |
| spelling | doaj.art-94db4fa0cf0740cd9e048040dc1976f92024-04-03T09:57:08ZengUniversity of BaghdadJournal of Engineering1726-40732520-33392024-03-0110310.31026/j.eng.2004.03.06DESIGN AND IMPLEMENTATION OF A DIGITAL PHASE LOCKED LOOP FREQUENCY SYNTHESIZER IN THE L BANDNasser N. Khamiss AI- AniWalid A. MahmoudRiadh A. Mahdy This paper proposes a design and implementation method of DPLL frequency synthesizer system. Such a system offers many advantages such as minimum complex architecture, low power consumption, and a maximum use of large scale integration technology. It can be used in many applications as cordless telephones, rnobile radios and other wireless products. A (2.4 - 3.6) GHz frequency range is designed and implemented with a 100KHz frequency step size. A spurious output levels of -70 dBc, an output power should be greater than 10 dBm, and a phase noise less then (-100) dBc/Hz at 100 kHz ofl'set from the carier are considered in our design. The channel selection is guided by digital gating circuits with thumbwheel switches. An option of PI\4 modulation of 5 MHz FM bandwidth is also included. https://www.joe.uobaghdad.edu.iq/index.php/main/article/view/3401 |
| spellingShingle | Nasser N. Khamiss AI- Ani Walid A. Mahmoud Riadh A. Mahdy DESIGN AND IMPLEMENTATION OF A DIGITAL PHASE LOCKED LOOP FREQUENCY SYNTHESIZER IN THE L BAND Journal of Engineering |
| title | DESIGN AND IMPLEMENTATION OF A DIGITAL PHASE LOCKED LOOP FREQUENCY SYNTHESIZER IN THE L BAND |
| title_full | DESIGN AND IMPLEMENTATION OF A DIGITAL PHASE LOCKED LOOP FREQUENCY SYNTHESIZER IN THE L BAND |
| title_fullStr | DESIGN AND IMPLEMENTATION OF A DIGITAL PHASE LOCKED LOOP FREQUENCY SYNTHESIZER IN THE L BAND |
| title_full_unstemmed | DESIGN AND IMPLEMENTATION OF A DIGITAL PHASE LOCKED LOOP FREQUENCY SYNTHESIZER IN THE L BAND |
| title_short | DESIGN AND IMPLEMENTATION OF A DIGITAL PHASE LOCKED LOOP FREQUENCY SYNTHESIZER IN THE L BAND |
| title_sort | design and implementation of a digital phase locked loop frequency synthesizer in the l band |
| url | https://www.joe.uobaghdad.edu.iq/index.php/main/article/view/3401 |
| work_keys_str_mv | AT nassernkhamissaiani designandimplementationofadigitalphaselockedloopfrequencysynthesizerinthelband AT walidamahmoud designandimplementationofadigitalphaselockedloopfrequencysynthesizerinthelband AT riadhamahdy designandimplementationofadigitalphaselockedloopfrequencysynthesizerinthelband |