System-Level Leakage Power Estimation Model for ASIC Designs
With advances in CMOS- technology and sub-micron process, leakage power dissipation has become a critical design metric. To incorporate more functions, designs are getting complex, thereby increases leakage power dissipation. Low power design objective requires early exploration and estimation. In t...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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VSB-Technical University of Ostrava
2018-01-01
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| Series: | Advances in Electrical and Electronic Engineering |
| Subjects: | |
| Online Access: | http://advances.utc.sk/index.php/AEEE/article/view/2947 |
| _version_ | 1797826984226586624 |
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| author | Abhishek Narayan Tripathi Arvind Rajawat |
| author_facet | Abhishek Narayan Tripathi Arvind Rajawat |
| author_sort | Abhishek Narayan Tripathi |
| collection | DOAJ |
| description | With advances in CMOS- technology and sub-micron process, leakage power dissipation has become a critical design metric. To incorporate more functions, designs are getting complex, thereby increases leakage power dissipation. Low power design objective requires early exploration and estimation. In this paper, we present the power estimation models for ASIC (Application Specific Integrated Circuit) based designs at the C-level of abstraction. The method includes analysis and extraction of the application specific information from the LLVM (Low-Level Virtual Machine) bit-code; which further applies to train the neural network. The trained model is applied in the estimation of the leakage power. Estimation of design power using our models is compared to the implemented measurement, which demonstrates its accuracy. In addition, the proposed methodology is significantly quicker and abolishes the need of synthesis based exploration. |
| first_indexed | 2024-04-09T12:40:59Z |
| format | Article |
| id | doaj.art-9631e713a9724e22956b0f7d1d636710 |
| institution | Directory Open Access Journal |
| issn | 1336-1376 1804-3119 |
| language | English |
| last_indexed | 2024-04-09T12:40:59Z |
| publishDate | 2018-01-01 |
| publisher | VSB-Technical University of Ostrava |
| record_format | Article |
| series | Advances in Electrical and Electronic Engineering |
| spelling | doaj.art-9631e713a9724e22956b0f7d1d6367102023-05-14T20:50:12ZengVSB-Technical University of OstravaAdvances in Electrical and Electronic Engineering1336-13761804-31192018-01-0116336136610.15598/aeee.v16i3.29471005System-Level Leakage Power Estimation Model for ASIC DesignsAbhishek Narayan TripathiArvind RajawatWith advances in CMOS- technology and sub-micron process, leakage power dissipation has become a critical design metric. To incorporate more functions, designs are getting complex, thereby increases leakage power dissipation. Low power design objective requires early exploration and estimation. In this paper, we present the power estimation models for ASIC (Application Specific Integrated Circuit) based designs at the C-level of abstraction. The method includes analysis and extraction of the application specific information from the LLVM (Low-Level Virtual Machine) bit-code; which further applies to train the neural network. The trained model is applied in the estimation of the leakage power. Estimation of design power using our models is compared to the implemented measurement, which demonstrates its accuracy. In addition, the proposed methodology is significantly quicker and abolishes the need of synthesis based exploration.http://advances.utc.sk/index.php/AEEE/article/view/2947artificial neural network (ann)asicllvm ir (intermediate representation)power estimationsystem-level. |
| spellingShingle | Abhishek Narayan Tripathi Arvind Rajawat System-Level Leakage Power Estimation Model for ASIC Designs Advances in Electrical and Electronic Engineering artificial neural network (ann) asic llvm ir (intermediate representation) power estimation system-level. |
| title | System-Level Leakage Power Estimation Model for ASIC Designs |
| title_full | System-Level Leakage Power Estimation Model for ASIC Designs |
| title_fullStr | System-Level Leakage Power Estimation Model for ASIC Designs |
| title_full_unstemmed | System-Level Leakage Power Estimation Model for ASIC Designs |
| title_short | System-Level Leakage Power Estimation Model for ASIC Designs |
| title_sort | system level leakage power estimation model for asic designs |
| topic | artificial neural network (ann) asic llvm ir (intermediate representation) power estimation system-level. |
| url | http://advances.utc.sk/index.php/AEEE/article/view/2947 |
| work_keys_str_mv | AT abhisheknarayantripathi systemlevelleakagepowerestimationmodelforasicdesigns AT arvindrajawat systemlevelleakagepowerestimationmodelforasicdesigns |