| Summary: | For higher density of transistors in Integrated Circuit (IC), various scaling technologies have been introduced. In the light of the physical limit in advancing single-gate transistor architecture, the structural transition from planar device architecture toward 3D device architecture (of which the representative one is Fin-shaped Field-Effect Transistor, or FinFET) manifests itself. However, during fabrication, the unexpected process-induced random variations of the transistor’s electrical characteristics have become more extreme with aggressively scaling down the physical dimension of transistor as well as with evolving from 2D to 3D device structure. Consequently, accurate and rapid estimation of the random variations conditioned on the variation sources (e.g., LER, RDF, and WFV) is required. Recently, machine learning-based approaches were utilized to estimate the LER-induced variations, but they were highly dependent on modeling and evaluation assumptions (e.g., Gaussian or independence). To that end, firstly, we introduce a GAN-based framework for the estimation of process-induced random variations. Since GAN is free from distributional assumptions, this enables precise prediction and, more importantly, enables unified estimation, i.e., adaptable to various variation sources. Secondly, to achieve better generalization on unseen conditions, we additionally suggest a two-step learning strategy utilizing the latest Conditional GAN models. Thirdly, we introduce sample-based evaluation procedure which measures the difference between two sample sets from a probabilistic perspective. Finally, the evaluation results on LER and RDF/WFV datasets show that our GAN-based framework is computationally efficient and is able to generate synthetic samples similar to the TCAD simulated samples that contain random variations, both qualitatively and quantitatively. From such results, our GAN-based framework is expected to be successfully applied to real data, and consequently be able to reliably estimate the random variations of fabricated transistors with multiple orders of magnitude speed-up compared to the conventional TCAD simulation-based estimation.
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