Memristor-Based Loop Filter Design for Phase Locked Loop
The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various comp...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2019-07-01
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| Series: | Journal of Low Power Electronics and Applications |
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| Online Access: | https://www.mdpi.com/2079-9268/9/3/24 |
| _version_ | 1828115754336124928 |
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| author | Naheem Olakunle Adesina Ashok Srivastava |
| author_facet | Naheem Olakunle Adesina Ashok Srivastava |
| author_sort | Naheem Olakunle Adesina |
| collection | DOAJ |
| description | The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741−994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations. |
| first_indexed | 2024-04-11T12:45:14Z |
| format | Article |
| id | doaj.art-97331795b1774c3c945c41c6d4ba9c6c |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-11T12:45:14Z |
| publishDate | 2019-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-97331795b1774c3c945c41c6d4ba9c6c2022-12-22T04:23:22ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682019-07-01932410.3390/jlpea9030024jlpea9030024Memristor-Based Loop Filter Design for Phase Locked LoopNaheem Olakunle Adesina0Ashok Srivastava1Division of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803, USADivision of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803, USAThe main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741−994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations.https://www.mdpi.com/2079-9268/9/3/24filterhysteresis curvememristorphase locked loopvoltage controlled oscillator |
| spellingShingle | Naheem Olakunle Adesina Ashok Srivastava Memristor-Based Loop Filter Design for Phase Locked Loop Journal of Low Power Electronics and Applications filter hysteresis curve memristor phase locked loop voltage controlled oscillator |
| title | Memristor-Based Loop Filter Design for Phase Locked Loop |
| title_full | Memristor-Based Loop Filter Design for Phase Locked Loop |
| title_fullStr | Memristor-Based Loop Filter Design for Phase Locked Loop |
| title_full_unstemmed | Memristor-Based Loop Filter Design for Phase Locked Loop |
| title_short | Memristor-Based Loop Filter Design for Phase Locked Loop |
| title_sort | memristor based loop filter design for phase locked loop |
| topic | filter hysteresis curve memristor phase locked loop voltage controlled oscillator |
| url | https://www.mdpi.com/2079-9268/9/3/24 |
| work_keys_str_mv | AT naheemolakunleadesina memristorbasedloopfilterdesignforphaselockedloop AT ashoksrivastava memristorbasedloopfilterdesignforphaselockedloop |