A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC
This paper presents a 9-bit 1 GS/s successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the pseudo-pipeline operation is realized, which increases the sampling rate effectively. The ADC adopts two key technologies: the variable gain voltage-to-time...
Main Authors: | Suping Bai, Zhi Wan, Peiyuan Wan, Hongda Zhang, Yongkuo Ma, Xiaoyu Zhang, Xu Liu, Zhijie Chen |
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Format: | Article |
Language: | English |
Published: |
MDPI AG
2021-10-01
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Series: | Electronics |
Subjects: | |
Online Access: | https://www.mdpi.com/2079-9292/10/21/2650 |
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