An Asynchronous IEEE Floating-Point Arithmetic Unit
An asynchronous floating-point arithmetic unit is designed and tested at the transistor level usingCadence software. It uses CMOS (complementary metal oxide semiconductor) and DCVS (differentialcascode voltage switch) logic in a 0.35 µm process using a 3.3 V supply voltage, with dual-rail data ands...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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University of the Philippines
2007-12-01
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| Series: | Science Diliman |
| Subjects: | |
| Online Access: | http://journals.upd.edu.ph/index.php/sciencediliman/article/view/711 |
| Summary: | An asynchronous floating-point arithmetic unit is designed and tested at the transistor level usingCadence software. It uses CMOS (complementary metal oxide semiconductor) and DCVS (differentialcascode voltage switch) logic in a 0.35 µm process using a 3.3 V supply voltage, with dual-rail data andsingle-rail control signals using four-phase handshaking.Using 17,085 transistors, the unit handles single-precision (32-bit) addition/subtraction, multiplication,division, and remainder using the IEEE 754-1985 Standard for Binary Floating-Point Arithmetic, withrounding and other operations to be handled by separate hardware or software. Division and remainderare done using a restoring subtractive algorithm; multiplication uses an additive algorithm. Exceptionsare noted by flags (and not trap handlers) and the output is in single-precision.Previous work on asynchronous floating-point arithmetic units have mostly focused on single operationssuch as division. This is the first work to the authors' knowledge that can perform floating-point addition,multiplication, division, and remainder using a common datapath. |
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| ISSN: | 0115-7809 2012-0818 |