Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology

Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology

A 10‐bit pipelined analogue‐to‐digital converter (ADC) at a sampling rate of 100 MS/s utilising only metal–oxide–semiconductor (MOS) transistors is presented and designed in 1.8 V 0.18 μm standard digital complementary MOS (CMOS) n‐well technology. The internal gain of value 2 of the intermediate st...

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Bibliographic Details
Main Authors: Anil Singh, Veena Rawat, Alpana Agarwal
Format: Article
Language:English
Published: Hindawi-IET 2017-11-01
Series:IET Circuits, Devices and Systems
Subjects:
low-power pipelined ADC
digital CMOS technology
pipelined analogue-to-digital converter
metal-oxide-semiconductor transistors
MOS transistors
standard digital complementary n-well technology
Online Access:https://doi.org/10.1049/iet-cds.2016.0525

Internet

https://doi.org/10.1049/iet-cds.2016.0525

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