Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis
High-level synthesis has been widely recognized and accepted as an efficient compilation process targeting field-programmable gate arrays for algorithm evaluation and product prototyping. However, the massively parallel memory access demands and the extremely expensive cost of single-bank memory wit...
| Main Authors: | , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2018-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8270704/ |
| _version_ | 1818927743449956352 |
|---|---|
| author | Shouyi Yin Tianyi Lu Xianqing Yao Zhicong Xie Leibo Liu Shaojun Wei |
| author_facet | Shouyi Yin Tianyi Lu Xianqing Yao Zhicong Xie Leibo Liu Shaojun Wei |
| author_sort | Shouyi Yin |
| collection | DOAJ |
| description | High-level synthesis has been widely recognized and accepted as an efficient compilation process targeting field-programmable gate arrays for algorithm evaluation and product prototyping. However, the massively parallel memory access demands and the extremely expensive cost of single-bank memory with multi-port have impeded loop pipelining performance. Thus, based on an alternative multi-bank memory architecture, a joint approach that employs memory-aware force directed scheduling and multi-cycle memory partitioning is formally proposed to achieve legitimate pipelining kernel and valid bank mapping with less resource consumption and optimal pipelining performance. The experimental results over a variety of benchmarks show that our approach can achieve the optimal pipelining performance and meanwhile reduce the number of multiple independent memory banks by 49.2% on average, compared with the state-of-the-art approaches. |
| first_indexed | 2024-12-20T03:17:52Z |
| format | Article |
| id | doaj.art-9995a206634a46de9a95ec9f1acbe940 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-20T03:17:52Z |
| publishDate | 2018-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-9995a206634a46de9a95ec9f1acbe9402022-12-21T19:55:18ZengIEEEIEEE Access2169-35362018-01-0167526754010.1109/ACCESS.2018.27985868270704Multi-Bank Memory Aware Force Directed Scheduling for High-Level SynthesisShouyi Yin0Tianyi Lu1https://orcid.org/0000-0001-6388-3419Xianqing Yao2Zhicong Xie3Leibo Liu4Shaojun Wei5Institute of Microelectronics, Tsinghua University, Beijing, ChinaInstitute of Microelectronics, Tsinghua University, Beijing, ChinaInstitute of Microelectronics, Tsinghua University, Beijing, ChinaInstitute of Microelectronics, Tsinghua University, Beijing, ChinaInstitute of Microelectronics, Tsinghua University, Beijing, ChinaInstitute of Microelectronics, Tsinghua University, Beijing, ChinaHigh-level synthesis has been widely recognized and accepted as an efficient compilation process targeting field-programmable gate arrays for algorithm evaluation and product prototyping. However, the massively parallel memory access demands and the extremely expensive cost of single-bank memory with multi-port have impeded loop pipelining performance. Thus, based on an alternative multi-bank memory architecture, a joint approach that employs memory-aware force directed scheduling and multi-cycle memory partitioning is formally proposed to achieve legitimate pipelining kernel and valid bank mapping with less resource consumption and optimal pipelining performance. The experimental results over a variety of benchmarks show that our approach can achieve the optimal pipelining performance and meanwhile reduce the number of multiple independent memory banks by 49.2% on average, compared with the state-of-the-art approaches.https://ieeexplore.ieee.org/document/8270704/Modulo schedulingmemory partitioningmulti-bank memoryHLS |
| spellingShingle | Shouyi Yin Tianyi Lu Xianqing Yao Zhicong Xie Leibo Liu Shaojun Wei Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis IEEE Access Modulo scheduling memory partitioning multi-bank memory HLS |
| title | Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis |
| title_full | Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis |
| title_fullStr | Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis |
| title_full_unstemmed | Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis |
| title_short | Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis |
| title_sort | multi bank memory aware force directed scheduling for high level synthesis |
| topic | Modulo scheduling memory partitioning multi-bank memory HLS |
| url | https://ieeexplore.ieee.org/document/8270704/ |
| work_keys_str_mv | AT shouyiyin multibankmemoryawareforcedirectedschedulingforhighlevelsynthesis AT tianyilu multibankmemoryawareforcedirectedschedulingforhighlevelsynthesis AT xianqingyao multibankmemoryawareforcedirectedschedulingforhighlevelsynthesis AT zhicongxie multibankmemoryawareforcedirectedschedulingforhighlevelsynthesis AT leiboliu multibankmemoryawareforcedirectedschedulingforhighlevelsynthesis AT shaojunwei multibankmemoryawareforcedirectedschedulingforhighlevelsynthesis |