An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors
Herein, we present a noise shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) with an embedded passive gain multiplication technique. The noise shaping moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR). Th...
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MDPI AG
2022-01-01
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Online Access: | https://www.mdpi.com/1424-8220/22/3/869 |
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author | Changhyung Choi Jong-Wook Lee |
author_facet | Changhyung Choi Jong-Wook Lee |
author_sort | Changhyung Choi |
collection | DOAJ |
description | Herein, we present a noise shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) with an embedded passive gain multiplication technique. The noise shaping moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR). The proposed approach tackles the drawback of the previous active noise shaping (increased power and extra noise) and passive noise shaping (limited noise suppression and signal loss). Both noise shaping and gain multiplication are realized on-chip in an energy-efficient manner without an opamp. This approach uses only capacitors and switches in the finite impulse response (FIR) and infinite impulse response (IIR) filters. A comparator suppressing kickback noise is presented to handle the tradeoff between noise suppression and the filter capacitor size. The energy-efficient merged-capacitor switching (MCS) technique is effectively combined with rail-to-rail swing comparator and thermometer-coded capacitor array, which reduces the settling error in the digital to analog converter (DAC). The process-induced mismatch effect in the capacitive DAC is investigated using a behavioral model of the ADC. Additionally, we propose dynamic element matching (DEM) for the thermometer-coded capacitor array. The ADC is fabricated using a 0.18 μm CMOS process in an area of 0.26 mm<sup>2</sup>. Consuming 4.1 μW, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 66.5 dB and a spurious-free dynamic range (SFDR) of 79.1 dB. The figure-of-merit (FoM) of the ADC is 11.8 fJ/conversion-step. |
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institution | Directory Open Access Journal |
issn | 1424-8220 |
language | English |
last_indexed | 2024-03-09T23:09:58Z |
publishDate | 2022-01-01 |
publisher | MDPI AG |
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series | Sensors |
spelling | doaj.art-99bd057d70ee49adafd94c1a571b9e0e2023-11-23T17:46:44ZengMDPI AGSensors1424-82202022-01-0122386910.3390/s22030869An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT SensorsChanghyung Choi0Jong-Wook Lee1Information and Communication System-on-Chip (SoC) Research Center, School of Electronics and Information, Kyung Hee University, Yongin 17104, KoreaInformation and Communication System-on-Chip (SoC) Research Center, School of Electronics and Information, Kyung Hee University, Yongin 17104, KoreaHerein, we present a noise shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) with an embedded passive gain multiplication technique. The noise shaping moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR). The proposed approach tackles the drawback of the previous active noise shaping (increased power and extra noise) and passive noise shaping (limited noise suppression and signal loss). Both noise shaping and gain multiplication are realized on-chip in an energy-efficient manner without an opamp. This approach uses only capacitors and switches in the finite impulse response (FIR) and infinite impulse response (IIR) filters. A comparator suppressing kickback noise is presented to handle the tradeoff between noise suppression and the filter capacitor size. The energy-efficient merged-capacitor switching (MCS) technique is effectively combined with rail-to-rail swing comparator and thermometer-coded capacitor array, which reduces the settling error in the digital to analog converter (DAC). The process-induced mismatch effect in the capacitive DAC is investigated using a behavioral model of the ADC. Additionally, we propose dynamic element matching (DEM) for the thermometer-coded capacitor array. The ADC is fabricated using a 0.18 μm CMOS process in an area of 0.26 mm<sup>2</sup>. Consuming 4.1 μW, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 66.5 dB and a spurious-free dynamic range (SFDR) of 79.1 dB. The figure-of-merit (FoM) of the ADC is 11.8 fJ/conversion-step.https://www.mdpi.com/1424-8220/22/3/869analog-to-digital convertersuccessive approximation registernoise shapingsignal-to-noisecharge pump |
spellingShingle | Changhyung Choi Jong-Wook Lee An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors Sensors analog-to-digital converter successive approximation register noise shaping signal-to-noise charge pump |
title | An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors |
title_full | An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors |
title_fullStr | An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors |
title_full_unstemmed | An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors |
title_short | An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors |
title_sort | 11 8 fj conversion step noise shaping sar adc with embedded passive gain for energy efficient iot sensors |
topic | analog-to-digital converter successive approximation register noise shaping signal-to-noise charge pump |
url | https://www.mdpi.com/1424-8220/22/3/869 |
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