THE MINIMIZATING OF LOGICAL SCHEME FOR IMPLEMENTATION OF PSEUDO LRU BY INTER-TYPE TRANSITION IN TRIGGER STRUCTURES
The principle of program control means that the processor core turns to the main memory of the computer for operands or instructions. According to architectural features, operands are stored in data segments, and instructions are stored in code segments of the main memory. The operating system uses...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
National Aerospace University «Kharkiv Aviation Institute»
2020-04-01
|
| Series: | Радіоелектронні і комп'ютерні системи |
| Subjects: | |
| Online Access: | http://nti.khai.edu/ojs/index.php/reks/article/view/1119 |
| _version_ | 1797760507527036928 |
|---|---|
| author | Вадим Олексійович Пуйденко Вячеслав Сергійович Харченко |
| author_facet | Вадим Олексійович Пуйденко Вячеслав Сергійович Харченко |
| author_sort | Вадим Олексійович Пуйденко |
| collection | DOAJ |
| description | The principle of program control means that the processor core turns to the main memory of the computer for operands or instructions. According to architectural features, operands are stored in data segments, and instructions are stored in code segments of the main memory. The operating system uses both page memory organization and segment memory organization. The page memory organization is always mapped to the segment organization. Due to the cached packet cycles of the processor core, copies of the main memory pages are stored in the internal associative cache memory. The associative cache memory consists of three units: a data unit, a tag unit, and an LRU unit. The data unit stores operands or instructions, the tag unit contains fragments of address information, and the LRU unit contains the logic of policy for replacement of string. The missing event attracts LRU logic to decide for substitution of reliable string in the data unit of associative cache memory. The pseudo-LRU algorithm is a simple and better substitution policy among known substitution policies. Two options for the minimization of the hardware for replacement policy by the pseudo-LRU algorithm in q - directed associative cache memory is implemented. The transition from the trigger structure of the synchronous D-trigger to the trigger structure of the synchronous JK-trigger is carried out reasonably in both options. The first option of minimization is based on the sequence for updating of the by the algorithm pseudo LRU, which allows deleting of the combinational logic for updating bits of LRU unit. The second option of minimization is based on the sequence for changing of the q - index of direction, as the consequence for updating the bits of LRU unit by the algorithm pseudo LRU. It allows additionally reducing the number of memory elements. Both options of the minimization allow improving such characteristics as productivity and reliability of the LRU unit. |
| first_indexed | 2024-03-12T18:59:35Z |
| format | Article |
| id | doaj.art-9c123f6c17134b96839071d6d973350e |
| institution | Directory Open Access Journal |
| issn | 1814-4225 2663-2012 |
| language | English |
| last_indexed | 2024-03-12T18:59:35Z |
| publishDate | 2020-04-01 |
| publisher | National Aerospace University «Kharkiv Aviation Institute» |
| record_format | Article |
| series | Радіоелектронні і комп'ютерні системи |
| spelling | doaj.art-9c123f6c17134b96839071d6d973350e2023-08-02T06:43:39ZengNational Aerospace University «Kharkiv Aviation Institute»Радіоелектронні і комп'ютерні системи1814-42252663-20122020-04-0102334710.32620/reks.2020.2.031138THE MINIMIZATING OF LOGICAL SCHEME FOR IMPLEMENTATION OF PSEUDO LRU BY INTER-TYPE TRANSITION IN TRIGGER STRUCTURESВадим Олексійович Пуйденко0Вячеслав Сергійович Харченко1Харківський радіотехнічний коледж, ХарківНаціональний аерокосмічний університет ім. М. Є. Жуковського «Харківський авіаційний інститут», ХарківThe principle of program control means that the processor core turns to the main memory of the computer for operands or instructions. According to architectural features, operands are stored in data segments, and instructions are stored in code segments of the main memory. The operating system uses both page memory organization and segment memory organization. The page memory organization is always mapped to the segment organization. Due to the cached packet cycles of the processor core, copies of the main memory pages are stored in the internal associative cache memory. The associative cache memory consists of three units: a data unit, a tag unit, and an LRU unit. The data unit stores operands or instructions, the tag unit contains fragments of address information, and the LRU unit contains the logic of policy for replacement of string. The missing event attracts LRU logic to decide for substitution of reliable string in the data unit of associative cache memory. The pseudo-LRU algorithm is a simple and better substitution policy among known substitution policies. Two options for the minimization of the hardware for replacement policy by the pseudo-LRU algorithm in q - directed associative cache memory is implemented. The transition from the trigger structure of the synchronous D-trigger to the trigger structure of the synchronous JK-trigger is carried out reasonably in both options. The first option of minimization is based on the sequence for updating of the by the algorithm pseudo LRU, which allows deleting of the combinational logic for updating bits of LRU unit. The second option of minimization is based on the sequence for changing of the q - index of direction, as the consequence for updating the bits of LRU unit by the algorithm pseudo LRU. It allows additionally reducing the number of memory elements. Both options of the minimization allow improving such characteristics as productivity and reliability of the LRU unit.http://nti.khai.edu/ojs/index.php/reks/article/view/1119алгоритм pseudo lru, тип тригерної структури, асоціативна кеш-пам'ять, блок lru, оцінка складності за квайном |
| spellingShingle | Вадим Олексійович Пуйденко Вячеслав Сергійович Харченко THE MINIMIZATING OF LOGICAL SCHEME FOR IMPLEMENTATION OF PSEUDO LRU BY INTER-TYPE TRANSITION IN TRIGGER STRUCTURES Радіоелектронні і комп'ютерні системи алгоритм pseudo lru, тип тригерної структури, асоціативна кеш-пам'ять, блок lru, оцінка складності за квайном |
| title | THE MINIMIZATING OF LOGICAL SCHEME FOR IMPLEMENTATION OF PSEUDO LRU BY INTER-TYPE TRANSITION IN TRIGGER STRUCTURES |
| title_full | THE MINIMIZATING OF LOGICAL SCHEME FOR IMPLEMENTATION OF PSEUDO LRU BY INTER-TYPE TRANSITION IN TRIGGER STRUCTURES |
| title_fullStr | THE MINIMIZATING OF LOGICAL SCHEME FOR IMPLEMENTATION OF PSEUDO LRU BY INTER-TYPE TRANSITION IN TRIGGER STRUCTURES |
| title_full_unstemmed | THE MINIMIZATING OF LOGICAL SCHEME FOR IMPLEMENTATION OF PSEUDO LRU BY INTER-TYPE TRANSITION IN TRIGGER STRUCTURES |
| title_short | THE MINIMIZATING OF LOGICAL SCHEME FOR IMPLEMENTATION OF PSEUDO LRU BY INTER-TYPE TRANSITION IN TRIGGER STRUCTURES |
| title_sort | minimizating of logical scheme for implementation of pseudo lru by inter type transition in trigger structures |
| topic | алгоритм pseudo lru, тип тригерної структури, асоціативна кеш-пам'ять, блок lru, оцінка складності за квайном |
| url | http://nti.khai.edu/ojs/index.php/reks/article/view/1119 |
| work_keys_str_mv | AT vadimoleksíjovičpujdenko theminimizatingoflogicalschemeforimplementationofpseudolrubyintertypetransitionintriggerstructures AT vâčeslavsergíjovičharčenko theminimizatingoflogicalschemeforimplementationofpseudolrubyintertypetransitionintriggerstructures AT vadimoleksíjovičpujdenko minimizatingoflogicalschemeforimplementationofpseudolrubyintertypetransitionintriggerstructures AT vâčeslavsergíjovičharčenko minimizatingoflogicalschemeforimplementationofpseudolrubyintertypetransitionintriggerstructures |