Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing
Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, the Anti-Symmetric Prod...
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MDPI AG
2022-09-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/19/3118 |
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| author | Kasarla Satish Reddy Sowmya Madhavan Przemysław Falkowski-Gilski Parameshachari Bidare Divakarachari Arun Mathiyalagan |
| author_facet | Kasarla Satish Reddy Sowmya Madhavan Przemysław Falkowski-Gilski Parameshachari Bidare Divakarachari Arun Mathiyalagan |
| author_sort | Kasarla Satish Reddy |
| collection | DOAJ |
| description | Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, the Anti-Symmetric Product Coding (APC) and Odd Multiple Storage (OMS) modules are utilized to implement the reconfigurable FIR filter (RFIR–APC–OMS). Herein, the APC–OMS module is used to reduce the area of the RFIR architecture. The performance of the RFIR–APC–OMS is analyzed in terms of: area, power, delay, LUT, flip flop, slices, and frequency. RFIR–APC–OMS has reduced 3.44% of area compared to the existing RFIR architecture employing the Dynamic Reconfigurable Partial Product Generator (DRPPG) module. |
| first_indexed | 2024-03-09T21:51:04Z |
| format | Article |
| id | doaj.art-9c52be1209ee4544a15a9aeb945b5e2c |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T21:51:04Z |
| publishDate | 2022-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-9c52be1209ee4544a15a9aeb945b5e2c2023-11-23T20:06:35ZengMDPI AGElectronics2079-92922022-09-011119311810.3390/electronics11193118Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal ProcessingKasarla Satish Reddy0Sowmya Madhavan1Przemysław Falkowski-Gilski2Parameshachari Bidare Divakarachari3Arun Mathiyalagan4Department of Electronics and Communication Engineering, Hyderabad Institute of Technology and Management, Hyderabad 501401, IndiaDepartment of Electronics and Communication Engineering, Nitte Meenakshi Institute of Technology, Yelahanka, Bangalore 560064, IndiaFaculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology, Narutowicza 11/12, 80-233 Gdansk, PolandDepartment of Electronics and Communication Engineering, Nitte Meenakshi Institute of Technology, Yelahanka, Bangalore 560064, IndiaDepartment of Electronics and Communication Engineering, Panimalar Institute of Technology, Chennai 600123, IndiaNowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, the Anti-Symmetric Product Coding (APC) and Odd Multiple Storage (OMS) modules are utilized to implement the reconfigurable FIR filter (RFIR–APC–OMS). Herein, the APC–OMS module is used to reduce the area of the RFIR architecture. The performance of the RFIR–APC–OMS is analyzed in terms of: area, power, delay, LUT, flip flop, slices, and frequency. RFIR–APC–OMS has reduced 3.44% of area compared to the existing RFIR architecture employing the Dynamic Reconfigurable Partial Product Generator (DRPPG) module.https://www.mdpi.com/2079-9292/11/19/3118Anti-Symmetric Product CodingOdd Multiple StorageCarry Look ahead adderReconfigurable Finite Impulse ResponseWallace tree multiplierDynamic Reconfigurable Partial Product Generator |
| spellingShingle | Kasarla Satish Reddy Sowmya Madhavan Przemysław Falkowski-Gilski Parameshachari Bidare Divakarachari Arun Mathiyalagan Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing Electronics Anti-Symmetric Product Coding Odd Multiple Storage Carry Look ahead adder Reconfigurable Finite Impulse Response Wallace tree multiplier Dynamic Reconfigurable Partial Product Generator |
| title | Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing |
| title_full | Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing |
| title_fullStr | Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing |
| title_full_unstemmed | Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing |
| title_short | Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing |
| title_sort | efficient fpga implementation of an rfir filter using the apc oms technique with wtm for high throughput signal processing |
| topic | Anti-Symmetric Product Coding Odd Multiple Storage Carry Look ahead adder Reconfigurable Finite Impulse Response Wallace tree multiplier Dynamic Reconfigurable Partial Product Generator |
| url | https://www.mdpi.com/2079-9292/11/19/3118 |
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