A 78 dB 0.417 mW Second-Order NS SAR ADC with Dynamic Amplifier-Assisted Integrator

A 78 dB 0.417 mW Second-Order NS SAR ADC with Dynamic Amplifier-Assisted Integrator

The noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is an innovative hybrid structure that offers performance advantages. The NS-SAR ADC leverages the SAR ADC as its foundation and combines oversampling technology and noise-shaping technology found in Sig...

Full description

Bibliographic Details
Main Authors:	Dingkang Cui, Zhihai Wang, Mengqian Jiang, Zhijie Chen
Format:	Article
Language:	English
Published:	MDPI AG 2024-01-01
Series:	Electronics
Subjects:	analog-to-digital converters noise shaping successive approximation type oversampling
Online Access:	https://www.mdpi.com/2079-9292/13/2/371

Similar Items

Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC
by: Kihyun Kim, et al.
Published: (2021-10-01)

An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier
by: Lu Jie, et al.
Published: (2021-01-01)

A 16-Bit 1-MS/s Pseudo-Differential SAR ADC With Digital Calibration and DNL Enhancement Achieving 92 dB SNDR
by: Panpan Zhang, et al.
Published: (2019-01-01)

A 7.6-nW 1-kS/s 10-Bit SAR ADC for Biomedical Applications
by: Yunfeng Hu, et al.
Published: (2022-11-01)

Continuous-Time Pipelined ADC: A Breed of Continuous-Time ADCs for Wideband Data Conversion
by: Hajime Shibata
Published: (2023-01-01)

A 28 nm CMOS 10 bit 100 ms/s asynchronous SAR ADC with low-power switching procedure and timing-protection scheme
by: Tang, Fang, et al.
Published: (2022)

A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers
by: Hyeonsik Kim, et al.
Published: (2023-01-01)

Time-interleaved SAR ADC with background timing-skew calibration for UWB wireless communication in IoT systems
by: Seong, Kiho, et al.
Published: (2020)

High accuracy dual output voltage reference circuit for differential 10-bit successive approximation register analog to digital converter using 180nm technology
by: Yusuf, Siti Idzura
Published: (2020)

Low-Power SAR ADCs: Basic Techniques and Trends
by: Pieter Harpe
Published: (2022-01-01)

A Single-Amplifier Dual-Residue Pipelined-SAR ADC
by: Min-Jae Seo
Published: (2021-02-01)

A 13-Bit 1-MS/s SAR ADC With Completion-Aware Background Capacitor Mismatch Calibration
by: Sunghyun Bae, et al.
Published: (2023-01-01)

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques
by: Jae-Hun Lee, et al.
Published: (2018-10-01)

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors
by: Changhyung Choi, et al.
Published: (2022-01-01)

NEW METHOD OF ON-LINE SUCCESSIVE-APPROXIMATION ADC CALIBRATION
by: Serhii Zakharchenko, et al.
Published: (2022-06-01)

Design of Self-Calibration Comparator for 12-Bit SAR ADCs
by: Junlong Tang, et al.
Published: (2023-05-01)

A 12-b Subranging SAR ADC Using Detect-and-Skip Switching and Mismatch Calibration for Biopotential Sensing Applications
by: Cong Luong Nguyen, et al.
Published: (2022-05-01)

An 11-Bit 10 MS/s SAR ADC with C–R DAC Calibration and Comparator Offset Calibration
by: Hoyong Jung, et al.
Published: (2022-11-01)

A 16.5-μW 73.7-dB-SNDR Second-Order Fully Passive Noise-Shaping SAR ADC With a Hybrid Switching Procedure
by: Zheng Li, et al.
Published: (2023-01-01)

8-bit folding and interpolating ADC /
by: Ahmad Faisal Adnan, 1987-, et al.
Published: (2010)

A 121 dB SNDR Zoom ADC Using Dynamic Amplifier and Asynchronous SAR Quantizer
by: Yangchen Jia, et al.
Published: (2023-01-01)

8-bit folding and interpolating ADC [electronic resource] /
by: Ahmad Faisal Adnan, 1987-
Published: (2010)

Low-power high-speed ADCs for nanometer CMOS integration /
by: 185149 Cao, Zhiheng, et al.
Published: (2008)

Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion
by: Brandon M. Kelly, et al.
Published: (2019-08-01)

A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS
by: Xianshan Wen, et al.
Published: (2024-01-01)

A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC
by: Peiyuan Wan, et al.
Published: (2020-01-01)

Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA
by: Juan David Espitia Castillo, et al.
Published: (2022-02-01)

A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications
by: Vishal Saxena, et al.
Published: (2012-07-01)

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications
by: Khuram Shehzad, et al.
Published: (2021-03-01)

Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs
by: Dongyang Jiang, et al.
Published: (2021-01-01)

Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems
by: Kiho Seong, et al.
Published: (2020-04-01)

A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier
by: Juyong Lee, et al.
Published: (2021-08-01)

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm
by: William Bontems, et al.
Published: (2023-02-01)

Systematization and Comparison of the Binary Successive Approximation Variants
by: Konrad Jurasz, et al.
Published: (2021-12-01)

A single-channel voltage-scalable 8-GS/s 8-b > 37.5-dB SNDR time-domain ADC with asynchronous pipeline successive approximation in 28-nm CMOS
by: Chen, Qian, et al.
Published: (2023)

High-resolution IF-to-baseband sigmadelta ADC for car radios /
by: 216840 Silva, Paulo G. R., et al.
Published: (2008)

A Data Weight Averaging-Inspired Digital Calibration Method for a 10-Bit Noise-Shaping Successive Approximation Register
by: Shuang Xie, et al.
Published: (2023-07-01)

Switched-Capacitor Techniques For High-Accuracy Filter And ADC Design [electronic resource]: /
by: 420703 Quinn, Patrick J, et al.
Published: (2007)

A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC
by: Suping Bai, et al.
Published: (2021-10-01)

A 1.25 MHz, 108 dB Chopped Sampling-Mixer-Based Impedance Spectroscopy SoC in 0.18-<inline-formula><math display="inline"><semantics><mrow><mrow><mi mathvariant="sans-serif">μ</mi><mi mathvariant="normal">m</mi></mrow></mrow></semantics></math></inline-formula> CMOS
by: Hyeonsik Kim, et al.
Published: (2022-12-01)