Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edg...
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| Format: | Article |
| Language: | English |
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MDPI AG
2015-05-01
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| Series: | Journal of Low Power Electronics and Applications |
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| Online Access: | http://www.mdpi.com/2079-9268/5/2/101 |
| _version_ | 1798034596896440320 |
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| author | Yin-Nien Chen Chien-Ju Chen Ming-Long Fan Vita Pi-Ho Hu Pin Su Ching-Te Chuang |
| author_facet | Yin-Nien Chen Chien-Ju Chen Ming-Long Fan Vita Pi-Ho Hu Pin Su Ching-Te Chuang |
| author_sort | Yin-Nien Chen |
| collection | DOAJ |
| description | In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices. |
| first_indexed | 2024-04-11T20:46:33Z |
| format | Article |
| id | doaj.art-9c5c3044a4a149f2a745d1ee16c2331c |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-11T20:46:33Z |
| publishDate | 2015-05-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-9c5c3044a4a149f2a745d1ee16c2331c2022-12-22T04:04:00ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682015-05-015210111510.3390/jlpea5020101jlpea5020101Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA CircuitsYin-Nien Chen0Chien-Ju Chen1Ming-Long Fan2Vita Pi-Ho Hu3Pin Su4Ching-Te Chuang5Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, 1001 University Road, Hsinchu 300, TaiwanDepartment of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, 1001 University Road, Hsinchu 300, TaiwanDepartment of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, 1001 University Road, Hsinchu 300, TaiwanDepartment of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, 1001 University Road, Hsinchu 300, TaiwanDepartment of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, 1001 University Road, Hsinchu 300, TaiwanDepartment of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, 1001 University Road, Hsinchu 300, TaiwanIn this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices.http://www.mdpi.com/2079-9268/5/2/101tunnel FET (TFET)FinFETwork function variation (WFV)line-edge-roughness (LER)carry-lookahead adder (CLA) |
| spellingShingle | Yin-Nien Chen Chien-Ju Chen Ming-Long Fan Vita Pi-Ho Hu Pin Su Ching-Te Chuang Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits Journal of Low Power Electronics and Applications tunnel FET (TFET) FinFET work function variation (WFV) line-edge-roughness (LER) carry-lookahead adder (CLA) |
| title | Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits |
| title_full | Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits |
| title_fullStr | Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits |
| title_full_unstemmed | Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits |
| title_short | Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits |
| title_sort | impacts of work function variation and line edge roughness on tfet and finfet devices and 32 bit cla circuits |
| topic | tunnel FET (TFET) FinFET work function variation (WFV) line-edge-roughness (LER) carry-lookahead adder (CLA) |
| url | http://www.mdpi.com/2079-9268/5/2/101 |
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