A performance-centric ML-based multi-application mapping technique for regular Network-on-Chip
This research article discusses the challenges faced by the Network-on-Chip (NoC) architecture due to increased integration density and proposes a novel fault-tolerant multi-application mapping approach called ”FANC.” The approach is based on Machine Learning (ML) and can provide solutions for unsee...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2023-07-01
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| Series: | Memories - Materials, Devices, Circuits and Systems |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2773064623000361 |
| _version_ | 1797796067614392320 |
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| author | Jitesh Choudhary Chitrapu Sai Sudarsan Soumya J. |
| author_facet | Jitesh Choudhary Chitrapu Sai Sudarsan Soumya J. |
| author_sort | Jitesh Choudhary |
| collection | DOAJ |
| description | This research article discusses the challenges faced by the Network-on-Chip (NoC) architecture due to increased integration density and proposes a novel fault-tolerant multi-application mapping approach called ”FANC.” The approach is based on Machine Learning (ML) and can provide solutions for unseen graphs and topologies without prior training. The proposed technique uses an ML-based model to extract relevant information from the search data and incorporate it into the search process. This results in a more robust model with a higher convergence rate and solution quality. The approach is evaluated using a variety of simulation parameters, such as communication cost, network latency, throughput, and power usage. Static simulations are performed in a Python programming environment, while dynamic simulations are performed with a SystemC-based cycle-accurate NoC simulator and the Orion2.0 Power tool. The results show that FANC reduces communication costs by 266%. It also improves network latency by 9%, throughput by 1%, and power consumption by 7%. The approach also simplifies and minimizes the search area in the design exploration process and can be used as an auxiliary component for other optimization algorithms. |
| first_indexed | 2024-03-13T03:27:33Z |
| format | Article |
| id | doaj.art-9cb083d1b4f74435a796a913437b5dd4 |
| institution | Directory Open Access Journal |
| issn | 2773-0646 |
| language | English |
| last_indexed | 2024-03-13T03:27:33Z |
| publishDate | 2023-07-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Memories - Materials, Devices, Circuits and Systems |
| spelling | doaj.art-9cb083d1b4f74435a796a913437b5dd42023-06-25T04:45:14ZengElsevierMemories - Materials, Devices, Circuits and Systems2773-06462023-07-014100059A performance-centric ML-based multi-application mapping technique for regular Network-on-ChipJitesh Choudhary0Chitrapu Sai Sudarsan1Soumya J.2BITS-Pilani, Hyderabad Campus, Hyderabad, India; Centre for Development of Advanced Computing, India; Corresponding author at: BITS-Pilani, Hyderabad Campus, Hyderabad, India.BITS-Pilani, Hyderabad Campus, Hyderabad, IndiaBITS-Pilani, Hyderabad Campus, Hyderabad, IndiaThis research article discusses the challenges faced by the Network-on-Chip (NoC) architecture due to increased integration density and proposes a novel fault-tolerant multi-application mapping approach called ”FANC.” The approach is based on Machine Learning (ML) and can provide solutions for unseen graphs and topologies without prior training. The proposed technique uses an ML-based model to extract relevant information from the search data and incorporate it into the search process. This results in a more robust model with a higher convergence rate and solution quality. The approach is evaluated using a variety of simulation parameters, such as communication cost, network latency, throughput, and power usage. Static simulations are performed in a Python programming environment, while dynamic simulations are performed with a SystemC-based cycle-accurate NoC simulator and the Orion2.0 Power tool. The results show that FANC reduces communication costs by 266%. It also improves network latency by 9%, throughput by 1%, and power consumption by 7%. The approach also simplifies and minimizes the search area in the design exploration process and can be used as an auxiliary component for other optimization algorithms.http://www.sciencedirect.com/science/article/pii/S2773064623000361Fault-tolerantNeural networkNetwork-on-ChipMachine LearningMulti-application mapping |
| spellingShingle | Jitesh Choudhary Chitrapu Sai Sudarsan Soumya J. A performance-centric ML-based multi-application mapping technique for regular Network-on-Chip Memories - Materials, Devices, Circuits and Systems Fault-tolerant Neural network Network-on-Chip Machine Learning Multi-application mapping |
| title | A performance-centric ML-based multi-application mapping technique for regular Network-on-Chip |
| title_full | A performance-centric ML-based multi-application mapping technique for regular Network-on-Chip |
| title_fullStr | A performance-centric ML-based multi-application mapping technique for regular Network-on-Chip |
| title_full_unstemmed | A performance-centric ML-based multi-application mapping technique for regular Network-on-Chip |
| title_short | A performance-centric ML-based multi-application mapping technique for regular Network-on-Chip |
| title_sort | performance centric ml based multi application mapping technique for regular network on chip |
| topic | Fault-tolerant Neural network Network-on-Chip Machine Learning Multi-application mapping |
| url | http://www.sciencedirect.com/science/article/pii/S2773064623000361 |
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