Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA
This work presents an efficient implementation of the AES (Advance Encryption Standard) based on Tbox/T-1-box design for both the encryption and decryption on FPGA (Field Programmable Gate Array). The proposed architecture not only make efficient use of full capacity of dedicated 32 Kb BRAM (Block R...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Mehran University of Engineering and Technology
2015-10-01
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| Series: | Mehran University Research Journal of Engineering and Technology |
| Subjects: | |
| Online Access: | http://publications.muet.edu.pk/research_papers/pdf/pdf1153.pdf |
| Summary: | This work presents an efficient implementation of the AES (Advance Encryption Standard) based on Tbox/T-1-box design for both the encryption and decryption on FPGA (Field Programmable Gate Array). The proposed architecture not only make efficient use of full capacity of dedicated 32 Kb BRAM (Block RAM) of latest Xilinx FPGAs (Virtex-5, Virtex-6 and 7 Series) but also saves considerable amount of BRAM and logical resources by using multiple accesses from single BRAM in one cycle of system clock as compared to conventional LUT (Look-Up-Table) techniques. The proposed T-box/T-1-box based AES design for both the encryption and decryption fits into just 4 BRAMs on FPGA and results in good efficiency TPS (Throughput per Slice) with less power consumption. |
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| ISSN: | 0254-7821 2413-7219 |