Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA
This work presents an efficient implementation of the AES (Advance Encryption Standard) based on Tbox/T-1-box design for both the encryption and decryption on FPGA (Field Programmable Gate Array). The proposed architecture not only make efficient use of full capacity of dedicated 32 Kb BRAM (Block R...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Mehran University of Engineering and Technology
2015-10-01
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| Series: | Mehran University Research Journal of Engineering and Technology |
| Subjects: | |
| Online Access: | http://publications.muet.edu.pk/research_papers/pdf/pdf1153.pdf |
| _version_ | 1818190048266289152 |
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| author | Dur-e-Shahwar Kundi Arshad Aziz |
| author_facet | Dur-e-Shahwar Kundi Arshad Aziz |
| author_sort | Dur-e-Shahwar Kundi |
| collection | DOAJ |
| description | This work presents an efficient implementation of the AES (Advance Encryption Standard) based on Tbox/T-1-box design for both the encryption and decryption on FPGA (Field Programmable Gate Array). The proposed architecture not only make efficient use of full capacity of dedicated 32 Kb BRAM (Block RAM) of latest Xilinx FPGAs (Virtex-5, Virtex-6 and 7 Series) but also saves considerable amount of BRAM and logical resources by using multiple accesses from single BRAM in one cycle of system clock as compared to conventional LUT (Look-Up-Table) techniques. The proposed T-box/T-1-box based AES design for both the encryption and decryption fits into just 4 BRAMs on FPGA and results in good efficiency TPS (Throughput per Slice) with less power consumption. |
| first_indexed | 2024-12-11T23:52:31Z |
| format | Article |
| id | doaj.art-9d13b08c6d4745b7841ace417e0e8940 |
| institution | Directory Open Access Journal |
| issn | 0254-7821 2413-7219 |
| language | English |
| last_indexed | 2024-12-11T23:52:31Z |
| publishDate | 2015-10-01 |
| publisher | Mehran University of Engineering and Technology |
| record_format | Article |
| series | Mehran University Research Journal of Engineering and Technology |
| spelling | doaj.art-9d13b08c6d4745b7841ace417e0e89402022-12-22T00:45:27ZengMehran University of Engineering and TechnologyMehran University Research Journal of Engineering and Technology0254-78212413-72192015-10-01344441446Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGADur-e-Shahwar Kundi 0Arshad Aziz 1Department of Electrical Engineering, National University of Sciences & Technology, Islamabad, PakistanDepartment of Electrical Engineering, National University of Sciences & Technology, Islamabad, PakistanThis work presents an efficient implementation of the AES (Advance Encryption Standard) based on Tbox/T-1-box design for both the encryption and decryption on FPGA (Field Programmable Gate Array). The proposed architecture not only make efficient use of full capacity of dedicated 32 Kb BRAM (Block RAM) of latest Xilinx FPGAs (Virtex-5, Virtex-6 and 7 Series) but also saves considerable amount of BRAM and logical resources by using multiple accesses from single BRAM in one cycle of system clock as compared to conventional LUT (Look-Up-Table) techniques. The proposed T-box/T-1-box based AES design for both the encryption and decryption fits into just 4 BRAMs on FPGA and results in good efficiency TPS (Throughput per Slice) with less power consumption.http://publications.muet.edu.pk/research_papers/pdf/pdf1153.pdfAdvance Encryption StandardBRAMField Programmable Gate ArrayT-Box/T-1-Box |
| spellingShingle | Dur-e-Shahwar Kundi Arshad Aziz Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA Mehran University Research Journal of Engineering and Technology Advance Encryption Standard BRAM Field Programmable Gate Array T-Box/T-1-Box |
| title | Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA |
| title_full | Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA |
| title_fullStr | Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA |
| title_full_unstemmed | Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA |
| title_short | Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA |
| title_sort | implementation of t box t 1 box based aes design on latest xilinx fpga |
| topic | Advance Encryption Standard BRAM Field Programmable Gate Array T-Box/T-1-Box |
| url | http://publications.muet.edu.pk/research_papers/pdf/pdf1153.pdf |
| work_keys_str_mv | AT dureshahwarkundi implementationoftboxt1boxbasedaesdesignonlatestxilinxfpga AT arshadaziz implementationoftboxt1boxbasedaesdesignonlatestxilinxfpga |