A 17-level quadruple boost switched-capacitor inverter with reduced devices and limited charge current
Abstract In this paper, a quadruple boost switched-capacitor multi-level inverter is proposed. The proposed structure utilizes a DC source, 11 switches, and a diode to achieve 17-level output voltage levels. This structure consists of three capacitors with the ability for self-balancing voltages. Th...
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| Format: | Article |
| Language: | English |
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Nature Portfolio
2024-03-01
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| Series: | Scientific Reports |
| Online Access: | https://doi.org/10.1038/s41598-024-56717-8 |
| _version_ | 1827316066199535616 |
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| author | Majid Hosseinpour Masoumeh Derakhshandeh Ali Seifi Mahdi Shahparasti |
| author_facet | Majid Hosseinpour Masoumeh Derakhshandeh Ali Seifi Mahdi Shahparasti |
| author_sort | Majid Hosseinpour |
| collection | DOAJ |
| description | Abstract In this paper, a quadruple boost switched-capacitor multi-level inverter is proposed. The proposed structure utilizes a DC source, 11 switches, and a diode to achieve 17-level output voltage levels. This structure consists of three capacitors with the ability for self-balancing voltages. The capacitors achieve automatic voltage balancing through a series/parallel connection with the input voltage source. To control the switching pulses of the switches, level-shifted pulse width modulation (LS-PWM) strategy has been employed. A comparative evaluation has been performed between the proposed structure and structures presented in recent articles, considering various parameters such as voltage gain, number of DC sources, number of semiconductor devices, maximum blocking voltage (MBV), and total standing voltage (TSV). Considering this comparison, the lower number of semiconductor devices for generating a 17-level output with suitable voltage gain, and especially the cost-effectiveness of the structure, are the main advantages of the proposed configuration. In addition, a soft charging method has been employed to limit the inrush current of capacitors. Moreover, the power losses of the proposed structure have been investigated, indicating its acceptable efficiency. Finally, for the analysis and validation of the proposed structure's performance, an experimental prototype has been implemented and evaluated under various conditions. The results indicate satisfactory performance of the proposed structure under various stable and dynamic operating conditions. |
| first_indexed | 2024-04-24T23:08:19Z |
| format | Article |
| id | doaj.art-9d5419f4b0e8468fa3aec1a800d7c967 |
| institution | Directory Open Access Journal |
| issn | 2045-2322 |
| language | English |
| last_indexed | 2024-04-24T23:08:19Z |
| publishDate | 2024-03-01 |
| publisher | Nature Portfolio |
| record_format | Article |
| series | Scientific Reports |
| spelling | doaj.art-9d5419f4b0e8468fa3aec1a800d7c9672024-03-17T12:23:22ZengNature PortfolioScientific Reports2045-23222024-03-0114111710.1038/s41598-024-56717-8A 17-level quadruple boost switched-capacitor inverter with reduced devices and limited charge currentMajid Hosseinpour0Masoumeh Derakhshandeh1Ali Seifi2Mahdi Shahparasti3Department of Electrical and Computer Engineering, University of Mohaghegh ArdabiliDepartment of Electrical and Computer Engineering, University of Mohaghegh ArdabiliDepartment of Electrical and Computer Engineering, University of Mohaghegh ArdabiliSchool of Technology and Innovations, University of VaasaAbstract In this paper, a quadruple boost switched-capacitor multi-level inverter is proposed. The proposed structure utilizes a DC source, 11 switches, and a diode to achieve 17-level output voltage levels. This structure consists of three capacitors with the ability for self-balancing voltages. The capacitors achieve automatic voltage balancing through a series/parallel connection with the input voltage source. To control the switching pulses of the switches, level-shifted pulse width modulation (LS-PWM) strategy has been employed. A comparative evaluation has been performed between the proposed structure and structures presented in recent articles, considering various parameters such as voltage gain, number of DC sources, number of semiconductor devices, maximum blocking voltage (MBV), and total standing voltage (TSV). Considering this comparison, the lower number of semiconductor devices for generating a 17-level output with suitable voltage gain, and especially the cost-effectiveness of the structure, are the main advantages of the proposed configuration. In addition, a soft charging method has been employed to limit the inrush current of capacitors. Moreover, the power losses of the proposed structure have been investigated, indicating its acceptable efficiency. Finally, for the analysis and validation of the proposed structure's performance, an experimental prototype has been implemented and evaluated under various conditions. The results indicate satisfactory performance of the proposed structure under various stable and dynamic operating conditions.https://doi.org/10.1038/s41598-024-56717-8 |
| spellingShingle | Majid Hosseinpour Masoumeh Derakhshandeh Ali Seifi Mahdi Shahparasti A 17-level quadruple boost switched-capacitor inverter with reduced devices and limited charge current Scientific Reports |
| title | A 17-level quadruple boost switched-capacitor inverter with reduced devices and limited charge current |
| title_full | A 17-level quadruple boost switched-capacitor inverter with reduced devices and limited charge current |
| title_fullStr | A 17-level quadruple boost switched-capacitor inverter with reduced devices and limited charge current |
| title_full_unstemmed | A 17-level quadruple boost switched-capacitor inverter with reduced devices and limited charge current |
| title_short | A 17-level quadruple boost switched-capacitor inverter with reduced devices and limited charge current |
| title_sort | 17 level quadruple boost switched capacitor inverter with reduced devices and limited charge current |
| url | https://doi.org/10.1038/s41598-024-56717-8 |
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